Shielding and Guarding:  AN-347-Analog Device Application Notes  (added 2/06)  How to Exclude Interference-Type Noise.What to do and Why to do it- A Rational Approach

Simplified Analysis of Phase-Locked Loop Capture and Tracking Range (AN 1200-7):  Agilent Application Note   (Circuit / schematic design added 6/06)

Software PLL locks VCXO to reference :  08/03/98 EDN-Design Ideas  / (added 2/06)

Startup Time[comma] Profile Measurement of PLL VCOs and Crystal Oscillators:  National Semiconductor - Application Note   (added 2/06)

Tape and Reel Dimensions:  Analog Devices Application Notes  (added2/06) 

TB042: Interfacing a KEELOQ® Encoder to a PLL Circuit:  Microchip Application Note - Published 19-Mar-01   (added 2/06)

TB078: PLL Jitter and Its Effects in the CAN Protocol:  Microchip Application Note - Published 15-Jun-04   (added 2/06)

The Phase Locked Loop IC as a Communication System Building Block:  National Semiconductor - Application Note   (added 2/06)

Two gates and a microprocessor form digital PLL:  04/14/05 EDN Design Ideas  / (added 2/06)  Low-frequency PLL needs just a processor and gates.

Unlocked PLL Retains Locked Frequency:  07/20/95 EDN-Design Ideas / (Electronic Circuit diagram added 03/03) Using the PC2 in-phase comparator output, the circuit in Fig 1 keeps the unlocked, or free-run, frequency of a 74HC4046 PLL near the locked frequency. With no signal input, the VCO output normally adjusts to its lowest frequency (one-half the locked frequency, f0). In some applications, such a large frequency excursion may be undesirable. With the addition of D1, R3, C2, R4, and the 74HC04 inverting buffer, the free-run frequency remains near the locked frequency in the absence of a signal input....