Here's one for the students. Suppose I'm using an FPGA or a CPLD with D flipflops and AND/OR/Inverter logic resources. I want to make two different kinds of JK flipflops, one with set dominant over reset and the other with reset dominant over set. How do I do this?

Not exactly sure what you are talking about...maybe a web search can help you out. Info.com is a great web search engine...be specific and u just might find your results u need.

I have made these two and other special versions of the "JK" flipflop before. I posted this question because it was one of my standard interview questions and I had always been surprised at how many EEs, especially FPGA designers, weren't familiar with feedback around a D flipflop. Much like a C programmer who isn't familiar with the underlying assembly language.

isnt that easy? just add an AND gate to each... so for when set is dominant, just have 'set' from outside world connected to 'set' input... and then inverted and connected to one input of the AND gate. Then have 'reset' from outside world into other input of AND gate. Then output of the AND gate goes to the 'reset' of the flip flop.

or have i got the wrong idea?

The feedback goes into the D input, the output of a two input OR gate. One OR input is J, the set input. If it is high Q goes high on the next clock edge irrespective of K the reset input or the current state of Q. The other OR input is the output of a two input AND gate with ine inverted input. The inverted input is K and the noninverted input is the Q output. If both J and K are low Q is fed back into D and the FF retains it's state. If K is high and J is low the D input is low and the FF is reset, so J is dominant over K. Now interchange the OR and AND
gates and think about the behaviour, the reset is dominant over the set input. You can expand the number of gates and inputs to get various things like clocked D FFs, multi-input JKs, gated T FFs etc. It's all based on D FFs and feedback.

If you had asked me how to make a gated odd-length ring counter with JK flip flops, I could have told you - but alas, I am a newbie and my head is still ringing dully after reading the thread. Are there any set dominant over reset or vice versa conditions in an odd or even length ring counter? If there are it would be a great teaching point to explain.


-T.