74ACT74 makes low-skeW clock
divider - 12/17/98 EDN Design Idea (File contains many circuits. Scroll to find this one. )
Serial-data systems often generate an internal clock at twice the data rate for mid-bit sampling or for
generating bi-phase codes. External equipment and some internal processes require a clock that runs at the data
rate. Simply dividing the twice-rate clock with a flip-flop generates a data-rate clock that is skewed by one
logic delay with respect to the input. This delay can be a significant fraction of the bit period. . . [by Tom
Napier, Consultant, North Wales, PA]
Amplifiers perform precision
divide-by-2 circuit - 03/06/03 EDN Design Idea Rotary encoder mates with digital potentiometer -
The classic implementation of a voltage-halving circuit uses two equal-value resistors. Using 1% resistors
provides a divider output with 2% accuracy. For most applications, this per. . . [by Glen Brisebois and Jon
Munson, Linear Technology Corp, Milpitas, CA]
Analog divider uses feW components -
01/04/07 EDN Design Idea Low-cost op amp, CMOS timer perform analog math. . . [by David Cripe, Chatham, IL]
Charge-pump circuit divides by two -
02/18/99 EDN Design Idea (Collection of Design Ideas, scroll to find this one) Small size and efficiency
approaching 100% make switched-capacitor charge pumps popular for voltage doubling and inverting in miniature
dc-dc applications. Few are aware, however, that most charge pumps can halve as well as double or invert an input
voltage. The increasing adoption of low-voltage logic makes this ÷2 capability useful for generating low-voltage
supplies in portable equipment. . . [by Budge Ing, Maxim Integrated Products, Sunnyvale, CA]
Cheap 40kHz Clock -
ASCII format. This circuit has worked for me in many applications. (it might be an idea to buffer the signal
befor using it. (There are still 5 unused gates in the 'C14) (electronic circuit added06/06/06) . . .
Circuit conditions
variable-duty-cycle clock - 02/17/97 EDN Design Idea Simple enhancement of an earlier Design Idea
("Delay line implements clock doubler", EDN, July 18, 1996, pg 102) implements a variable-duty-cycle clock-signal
conditioner. The circuit accepts an input clock of any duty cycle and. . . [by David Albean, Thomson Consumer
Electronics, Indianapolis, IN]
Circuit divides frequency by N+1 -
11-Jul-02 EDN Design Idea Digital frequency dividers usually use flip-flop stages that connect the Q pin to the
D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to
the input. You can divide any in. . . [by Bert Erickson, Fayetteville, NY]
Circuit Forms
Divide By 1.5 Counter - Two inexpensive ICs divide a TTL clock signal by 1. 5. By following the
circuit with another flip/flop, you could also generate a divide by three function . . . [Circuit by David
Johnson P.E., 07/06/00]
Clock divider - The 2x
trigger is a little involved, but here is a circuit that will do divide by two preserving pulse width. . .
[Vance Gloster]
Counter Provides Divide by 4.5
Function - 05/22/97 EDN Design Idea It's common practice to use a divide-by-N circuit to create a
free-running clock based on another clock source. Designing such a circuit where N is a no integer is not as
difficult as you might think. Listing 1 gives the synthesizable VHDL code to configure a divide-by-4.5circuit.
Figure 1 shows the simulation result for a 50-MHz input clock and a 11. 11-MHz output. You can apply the concept
given here for any N, where N is 1. 5, 2. 5, 3.5. First, consider what divide-by-4.5is. It simply means that, for
every nine clocks, you need to generate two symmetrical pulses. . . [by Alex Sumarsono, Baynetworks Inc, San
Jose, CA]
Divide a TTL
Clock Signal by 1.5 - A TTL clock signal by 1.5is divided by 2 inexpensive Ics. When this circuit is
followed with another flip/flop, a divide-by-3 funtion is generated . . . [Hobby Circuit designed by Dave Johnson
P.E., 07/06/00]
Divide By 1.5
Counter - Two inexpensive ICs divide a TTL clock signal by 1. 5. By following the circuit with
another flip/flop, you could also generate a divide by three function . . . [Circuit by Dave Johnson P.E.,
07/06/00]
Divide Frequency by N+1 -
11-Jul-02 EDN Design Idea Digital frequency dividers usually use flip-flop stages that connect the Q pin to the
D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to
the input. You can divide any in. . . [by Bert Erickson, Fayetteville, NY]
Frequency Dividers -
This paper is a collection of unusual frequency divider techniques which offer features not achieved with
ordinary divider ICs or prescalers. . . [Charles Wenzel (unless otherwise noted)]
Precision divide-by-two analog
attenuator needs no external components - 03/17/05 EDN Design Idea Many modern A/D converters
offer only a 5V input range, and using these converters with a 65V or larger input signal gives the designer a
problem how to discard half of a good analog signal without introducing errors and distortion. . . [by Moshe
Gerstanhaber and Chau Tran, Analog Devices, Wilmington, MA]
Simple Divide-By-N using 161
series chip - Timing and oscillator circuit diagrams / circuit schematics. . .
Synthesize optimal
digital-frequency dividers - 05/13/99 EDN Design Idea For many applications, you need to divide a
reference clock into one or more subclocks to use in different parts of the system. Sometimes, . PDF contains
many circuits, scroll to find this one. . . [by Lindo St Angel, PrairieComm Inc, Arlington Heights, IL]
Unusual Frequency Dividers -
This paper is a collection of unusual frequency divider techniques which offer features not achieved with
ordinary divider ICs or prescalers. . . [Charles Wenzel (unless otherwise noted)]
Unusual frequency dividers -
Timing and oscillator circuit diagrams / circuit schematics. . . |