Circuit conditions variable-duty-cycle clock - 02/17/97 EDN-Design Ideas Simple enhancement of an earlier Design Idea("Delay line implements clock doubler",EDN, July 18, 1996, pg 102) implements a variable-duty-cycle clock-signal conditioner. The circuit accepts an input clock of any duty cycle and generates any desired duty cycle at the output. You need to add only one flip-flop to the earlier design to generate an arbitrary-duty-cycle output. You can use the circuit to correct a non-50% input to a 50% output or to create a non-50% output from any arbitrary input duty cycle__ Circuit Design by David Albean, Thomson Consumer Electronics, Indianapolis, IN Circuit divides frequency by N+1 - 07/11/02 EDN-Design Ideas Digital frequency dividers usually use flip-flop stages that connect the Q pin to the D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to the input. You can divide any integer lower than 2N with minimal stages, where N is the number of stages__ Circuit Design by Bert Erickson, Fayetteville, NY
Circuit divides frequency by N+5 - 07/11/02 EDN-Design Ideas Digital frequency dividers usually use flip-flop stages that connect the Q pin to the D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to the input. You can divide any integer lower than 2N with minimal stages, where N is the number of stages__ Circuit Design by Bert Erickson, Fayetteville, NY
Circuit Forms Divide By 1.5 Counter - Two inexpensive ICs divide a TTL clock signal by 1.5. By following the circuit with another flip/flop, you could also generate a divide by three function. . . Circuit by David Johnson P.E.-July, 2000
Counter Provides Divide by 4.5 Function - 05/22/97 EDN-Design Ideas It's common practice to use a divide-by-N circuit to create a free-running clock based on another clock source. Designing such a circuit where N is a noninteger is not as difficult as you might think. Listing 1 gives the synthesizable VHDL code to configure a divide-by-4.5 circuit. Figure 1 shows the simulation result for a 50-MHz input clock and a 11.11-MHz output. You can apply the concept given here for any N, where N is 1.5, 2.5, 3.5. First, consider what divide-by-4.5 is. It simply means that, for every nine clocks, you need to generate two symmetrical pulses. __ Circuit Design by Alex Sumarsono, Baynetworks Inc, San Jose, CA
Dekatron-device used for dividing by 10 during the valve era - The circuit diagram is almost the same as Mike's. I added an ON/OFF switch and an additional toggle switch to stop the spin. The resistors are standard types (according to Mike I should've used higher power ones to ensure adequate voltage rating); the capacitors need to have sufficient voltage rating. I didn't have anything rated 400V so I used two 330nF capacitors in series in two places. __ Designed by Hans Summers
Divide a TTL Clock Signal by 1.5 - Two inexpensive ICs divide a TTL clock signal by 1.5. By following the circuit with another flip/flop, you could also generate a divide by three function . . . Hobby Circuit designed by Dave Johnson P.E.-July, 2000
Divide By 1.5 Counter - Two inexpensive ICs divide a TTL clock signal by 1.5. By following the circuit with another flip/flop, you could also generate a divide by three function. . . Circuit by Dave Johnson P.E.-July, 2000
Frequency Divider Adapts to I/O Condition - 12/05/96 EDN-Design Ideas The circuit in Figure 1 accepts an input clock signal, such as from a crystal oscillator, and divIdeas the frequency according to the input divisor word. You can easily modify the basic design of this versatile PLD-based divider to handle different I/O conditions. The design uses the FLEX8000 family of PLDs from Altera Corp (San Jose, CA). __ Circuit Design by Steve Hranilovic, University of Waterloo, Waterloo, ON, Canada
Frequency Dividers - This paper is a collection of unusual frequency divider techniques which offer features not achieved with ordinary divider ICs or prescalers __ Contact: Charles Wenzel of Wenzel Associates, Inc.
Frequency multiplier improves line readings - EDN-Design Ideas March 26, 1998 [ NOTE
: File has multiple design, scroll for this one.] Because of the low frequencies involved, accurately measuring line-frequency variations is complicated. When you use an ordinary frequency counter with a 1-sec gate time, the reading would be 59, 60, or 61 Hz. To obtain 0.01-Hz accuracy, you must increase the gate time to 100 sec, a scale that most frequency counters do not offer.__ Circuit Design by Yongping Xia, Teldata Inc, Los Angeles, CA
Precision divide-by-two analog attenuator needs no external components - 03/17/05 EDN-Design Ideas Many modern A/D converters offer only a 5V input range, and using these converters with a 65V or larger input signal gives the designer a problem how to discard half of a good analog signal without introducing errors and distortion. To solve the problem, you can use an attenuator comprising two operational amplifiers and two resistors(Figure 1)__ Circuit Design by Moshe Gerstanhaber and Chau Tran, Analog Devices, Wilmington, MA
Synthesize optimal digital-frequency dividers - 05/13/99 EDN-Design Ideas For many applications, you need to divide a reference clock into one or more subclocks to use in different parts of the system. Sometimes,PDF contains many circuits, scroll to find this one. __ Circuit Design by Lindo St Angel, PrairieComm Inc, Arlington Heights, IL
Unusual Frequency Dividers - This paper is a collection of unusual frequency divider techniques which offer features not achieved with ordinary divider ICs or prescalers __ Contact: Charles Wenzel of Wenzel Associates, Inc. |