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Memory Circuits

Last Updated: November 21, 2017 05:47 AM


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2-Phase, Spread Spectrum, DDR Memory Supplies with Ceramic Output Capacitors -  The LTC3776 is a 2-phase dual output synchronous stepdown switching regulator controller for DDR/QDR memory termination applications.  The second controller regulates its output voltage to 1/2 VREF while providing symmetrical source and sink output current capability.  __ Linear Technology/Analog Devices App Note, Jun 29th 2011

A Simple Circuit Surface Mount Flash Memory VPP Generator -  DN58 Design Notes__ Linear Technology/Analog Devices

Access odd memory locations without hardware -  05/27/99 EDN-Design Ideas - Some risc controllers, like the NEC V850 family, use an internal 32-bit architecture with an external 16-bit bus.  The architecture also allows interfaces with 8-bit memories.  HoweverPDF has several circuits, please scroll to find this one.    __ Circuit Design by Sorin Zarnescu, NEC Electronics, Santa Clara, CA

Adding external memory to Atmega128. Part 1. Schematic -  Atmel AVR microcontroller Atmega128 is equipped with internal 4Kbytes of SRAM memory.  Is it enough? Well it depends on what project it’s gonna hold.  If your project must deal with loads of data or run larger RTOS code you will definitely run

Adding external memory to Atmega128. Part 2. Software -  To test if external memory board works we are going to write a simple routine that tests if microcontroller can allocate memory heaps, write to and read from then.  First of all we have to set up AVRStudio project.  If your are going to use automated

An SD Card Music & Speech Recorder/Player -  This digital recorder stores WAV files on low-cost MMC/SD/SDHC cards.  It can be used as a jukebox, a sound effects player or an expandable "dicta-phone".  You can use it as a free-standing recorder or in conjunction with any Windows, Mac or Linux PC.__ SiliconChip

ATMEL 89 Series Flash Microcontroller Programmer Ver 2.0 -  This programmer was designed in view of to be flexible, economical and easy to built, the programmer hardware utilizes the standard TTL series parts and no special components are used.  The programmer is interfaced with the PC parallel port and there is no special requirement for the PC parallel port, so the older computers can also be used with this programmer __ Designed by Wichit Sirichote

Circuit gang-programs EEPROMs over I2C bus -  09/13/01 EDN-Design Ideas - You use the fully controlled circuit in Figure 1 to parallel-program two-wire serial EEPROMs via the I2C bus.  Gang programmers must address all memory devices during a write operation.  To verify the memory contents, however, the system must address only one memory at a time during read operations __ Circuit Design by Denisa Stefan, Catalyst Semiconductor, Sunnyvale, CA

DDR Memory Power Supply: 2.5V to 5.5Vin, 0.75V AT +/-6A Vtt, 0.75V AT 10mA Vref, 1MHz External Clock -  The LTC3617 is a high efficiency monolithic synchronous buck regulator utilizing a current mode, constant frequency architecture.  It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage equal to 0.5 • VDDQIN while sourcing and sinking up to 6A of load current.  An internal amplifier __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 2.5V to 5.5Vin, 1.25V AT +/-6A Vtt, 1.25V AT 10mA Vref, 2.25MHz -  The LTC3617 is a high efficiency monolithic synchronous buck regulator utilizing a current mode, constant frequency architecture.  It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage equal to 0.5 • VDDQIN while sourcing and sinking up to 6A of load current.  An internal amplifier __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 3.3Vin, 0.9V AT +/-3A Vtt (with 1.8V external reference) -  Many DDR termination applications require the bus termination voltage to be stepped down from a higher system voltage while tracking one-half of a reference voltage.  This option is allowable in most systems since a reference voltage is typically available.  This circuit shows a solution for a 3.3 V to 0.9V, ±3A termination __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 3.3Vin, 0.9V AT +/-3A Vtt, 1.8V AT 3A Vddq, 0.9V AT 10mA Vref -  The LTC3618 is a dual synchronous step-down regulator using a current mode, constant-frequency architecture.  It provides a complete DDR solution with an input voltage range from 2.25V to 5.5V.  The output of the first step-down regulator offers a high accuracy VDDQ supply.  A buffered reference generates VTTR at 50% of VDDQIN __ Linear Technology/Analog Devices App Note, Aug 8th 2011

DDR Memory Power Supply: 3.3Vin, 1.5V AT +/-3A Vtt (2.5V external reference) -  The LTC3413 is a high efficiency monolithic synchronous step-down DC/DC converter utilizing a constant frequency, current mode architecture.  It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage equal to  (0.5) VREF while sourcing or sinking up to 3A of output current.  An internal voltage __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 3.6V to 15Vin, 1.8V AT 3A Vddq, 0.9V AT +/-3A Vtt, 0.9V AT 10mA Vref -  The LTC3634 is a high efficiency, dual-channel monolithic synchronous step-down regulator which provides power supply and bus termination rails for DDR1, DDR2, and DDR3 SDRAM controllers.  The operating input voltage range is 3.6V to 15V, making it suitable for point-of-load power supply applications from a 5V or 12V input, __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 3.6V to 15Vin, VTT Powered from VDDQ -  The LTC3634 is a high efficiency, dual-channel monolithic synchronous step-down regulator which provides power supply and bus termination rails for DDR1, DDR2, and DDR3 SDRAM controllers.  The operating input voltage range is 3.6V to 15V, making it suitable for point-of-load power supply applications from a 5V or 12V input, __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 4V to 24Vin, 1.25V AT +/-10A Vtt (2.5V external reference) -  This circuit shows a ±10A design using LTC3717.  The input voltage can vary from 5V to 24V.  The input voltage can be below 5V if an external 5V bias is available for powering the VCC pin of LTC3717.  This design uses only two SO-8 PowerPak MOSFETs from Siliconix to deliver ±10A current.  To achieve a higher output current, use __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 5V to 28Vin, 1.5V AT +/-10A Vtt (3V external reference) -  The LTC3717 is a synchronous step-down switching regulator controller for double data rate  (DDR) and Quad Data Rate  (QDRTM) memory termination.  The controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor.  Operating frequency is selected by an external resistor __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR Memory Power Supply: 5Vin, 1.25V AT +/-6A Vtt (2.5V external reference) -  The LTC3831 is a high power, high efficiency switching regulator controller designed for DDR memory termination.  The LTC3831 generates an output voltage equal to 1/2 of an external supply or reference voltage.  The LTC3831 uses a synchronous switching architecture with N-channel MOSFETs.  Additionally, the chip senses output current __ Linear Technology/Analog Devices App Note, Jun 29th 2011

DDR3 1.5V VDDQ/20A 0.75VTT/±10A 4.5V to 14V Input -  The LTC3876 is a complete DDR power solution, compatible with DDR1, DDR2, DDR3 and future DDRX lower voltage standards.  The LTC3876 includes VDDQ and VTT DC/DC controllers and a precision linear VTT reference.  A differential output sense amplifier and precision internal reference combine to offer an accurate VDDQ supply.  The __ Linear Technology/Analog Devices App Note, Dec 5th 2011

DDR-differential-clock source on SOC drives two DDR-memory chips -  02/05/09  EDN-Design Ideas - OC integrates controller to drive two external-DDR-memory chips without a costly differential-clock buffer __ Circuit Design by Goh Ban Hok, Infineon Technologies, Singapore

DDS & converter form signal generator -  20-Feb-03 EDN-Design Ideas - Polarity protector outperforms Schottky diodes - Many applications require low-frequency signal generators that can deliver high-performance, high-resolution signals.  This design idea presents a circuit that generates frequencies of 0 to 1 MHz.  Sinusoidal, triangular, and square-wave outputs are available.  You can achieve frequency resolution of better than 0 __ Circuit Design by Colm Slattery, Analog Devices, Limerick, Ireland

DDS Device Produces Sawtooth Waveform -  10-Jul-03 EDN-Design Ideas - Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control.  Discrete components typically set the waveform frequency.  Unfortunately, drift in these component values over time and temperature limits the accuracy of the output frequency __ Circuit Design by Niamh Collins, Analog Devices, Limerick, Ireland

DDS Device provides Amplitude Modulation -  09/02/99 EDN-Design Ideas - Many applications require an analog output to assume different amplitudes, but many direct-digital-synthesis  (DDS) devices do not accommodate amplitude variations.  Test equipment uses DDS devices to generate signals of different frequencies.  However, the amplitude of these signals often must be variable, too.    __ Circuit Design by Mary McCarthy

DDS forms Inphase & Quadrature Generator -  12/04/97 EDN-Design Ideas - Many instrumentation applications use two sine waves to carry out coherent modulation.  The circuit in Figure 1 allows you to measure vector magnitudes  (for example, voltage or impedance) by multiplying the measured signal with inphase and quadrature sinusoidal signals of the same frequency.  In a classic approach, these signals come from one VCO and a pi/2  (90ş) delay.  However, when the measurements cover a wide frequency span, it is necessary to compensate phase differences between the measured and instrument circuits by using a programmable delay. __ Circuit Design by J Toda, R Bragos, and M Tresanchez, UPC, Barcelona, Spain

DDS Generates Precise PWM Waveforms -  10/02/03  EDN-Design Ideas - Pulse-width modulation is a simple way to modulate, or change, a square wave.  In its basic form, the duty cycle of the square wave changes according to some input.  The duty cycle is the ratio of high and low times in the square wave __ Circuit Design by Colm Slattery Analog Devices, Limerick, Ireland

DDS IC plus frequency-to-voltage converter make low-cost DA - C -  02/05/04  EDN-Design Ideas - Precision DACs are essential in many consumer, industrial, and military applications, but high-resolution DACs can be costly.  Frequency-to-voltage converters have good nonlinearity specifications—typically, 0.002% for the AD650—and  __ Circuit Design by Noel McNamara, Analog Devices, Limerick, Ireland

Design Provides Single-Port-To-Dual-Port SDRAM Converter -  EDN-Design Ideas -- 03/03/11    Read and write operations won't interfere with each other. __ Circuit Design by Yu-Chieh Chen, Instrument Technology Research Center, National Applied Research Laboratories, Hsinchu, Taiwan

Easy-To-Use Flash-Memory Modules Emulate Disk Drive -  09/01/94 EDN-Design Ideas - Because more and more flash-memory modules look just like familiar disk drives to your system, designing in fast and rugged mass storage has never been simpler.  Companies promoting the use of flash memory in mass-storage applications seem to have made an interesting discovery: To convince customers to use flash instead of a disk drive, make the flash look like a disk drive.  Increasingly, new flash storage products incorporate a hardware controller that emulates a disk drive's system interface.    __ Circuit Design by Gary Legg, Executive Editor 09/01/94

Embedded Memory Enhances Programmable Logic for Complex Designs -  11/07/96 EDN-Design Feature The growing densities of PLDs are making the chips suitable for increasingly complex designs.  Those designs require high-performance scratchpad RAM for temporary storage of data that passes through the logic circuitry that th __ Circuit Design by Rick Nelson, Contributing EDFtor

Fast, compact routine interfaces EEPROM to µC -  03/04/99 EDN-Design Ideas -  (Scroll to find this EDN    Design Idea)  __ Circuit Design by Grzegorz Mazur, Institute of Computer Science, Nowowiejska, Poland

FIFO Makes Cheap Waveform Generator -  12/21/95 EDN-Design Ideas - The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator.  IC1’s 82C54 produces the timebase for the wave table.  This IC can generate a 152-Hz to 5-MHz clock under software co __ Circuit Design by Todd Williams, Napco Security Systems Amityville, NY

FIFO provides data-width conversion -  09/26/02  EDN-Design Ideas - Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements.  However, in some applications, you need FIFO buffers for data conversion.  One example is the case in  __ Circuit Design by David Lou, Ghent University, Ghent, Belgium

FIR filter scheme saves ROM storage space -  05/11/95 EDN-Design Ideas - You can easily implement single-bit FIR filters using ROM look-up tables, which allows you to avoid costly multiplier accumulators.  Unfortunately, as filter order increases, so does the size of the ROM.  Fig 1 shows how you can reduce the storage requirement for larger-order filters.  The following difference equation defines an N-tap FIR filter, where y  (n) , x  (n-m) , and h  (m) are, respectively, the output sequence, the input sequence delayed by m samples, and the impulse response  (coefficients) of the filter: __ Circuit Design by CA Jalaludeen, Defence R&D Organisation, Kochi, Kerala, India

Flash Memory VPP Generator Reference Designs -  DN97 Design Notes__ Linear Technology/Analog Devices

Flash-Memory Modules Emulate Disk Drive -  09/01/94  EDN-Design Ideas - Because more and more flash-memory modules look just like familiar disk drives to your system, designing in fast and rugged mass storage has never been simpler.  Companies promoting the use of flash memory in mass-storage applications seem to have made an  __ Circuit Design by Gary Legg, Executive Editor

Graphics Controller Handles Interleaved Memory -  02/16/95 EDN-Design Ideas - The Intel 82786 graphics controller does not generate a proper data-transfer cycle if your video RAM  (VRAM) is organized into two interleaved banks  (Fig 1) .  The circuit in Fig 2 overcomes this device's deficiency. __ Circuit Design by YS Tam, Canadian Marconi Co, Kanata, ON, Canada

Hookup Increases Ad2101's Memory -  04/27/95 EDN-Design Ideas - The circuit in Fig 1 increases the memory of Analog Devices' 2101 family of fixed-point DSP µPs.  The simple scheme uses only three external static-memory devices and no glue logic.  With the additional memory, the DSP µP will have 16k words of program memory and 15k words of data memory.   (The memory totals include 2k words of internal program memory and 1k word of internal data memory.)  __ Circuit Design by Bogdan Morariu Digital Dispatch Systems, Richmond, BC, Canada

LTC3634 Dual 15V, 3A Monolithic Step-Down Regulator for DDR Power -  The LTC®3634 is a high efficiency, dual-channel monolithic synchronous step-down regulator which provides power supply and bus termination rails for DDR1, DDR2, and DDR3 SDRAM controllers.  The operating input voltage range is 3.6V to 15V, making it suitable for point-of-load power supply applications from a 5V or 12V input, __ Linear Technology/Analog Devices App Note, Jeff Gruetter-Senior Product Marketing Engineer Sep 21st 2011

LTC3676 8-Output PMIC for Application Processors-Video Product Brief -  The LTC®3676 is a complete power management solution for advanced portable application processor-based systems.  The device contains four synchronous step-down DC/DC converters for core, memory, I/O, and system on-chip  (SoC) rails and three 300mA LDO regulators for low noise analog supplies.  The LTC3676-1 has a ±1.5A __ Linear Technology/Analog Devices App Note, Steve Knoth-Senior Product Marketing Engineer, Power Products Oct 24th 2013

Multiplexers convert Deep FIFO buffer to bidirectional -  12/04/97 EDN-Design Ideas - Interfaces to digital data recorders often require deep FIFO buffers to match the system's data rate to the recorder rate.  Sometimes, a second set of FIFO buffers in the opposite direction handles playback data.  Doubling.    __ Circuit Design by Kevin Kelley, Telephonics Corp, Farmingdale, NY

PAL Powers Universal ISA Bus Interface -  02/02/95 EDN-Design Ideas - A pc board bearing the 16-bit ISA data-bus interface in Fig 1 can adapt automatically to either 8- or 16-bit motherboard slots.  The interface comprises three bidirectional octal buffers and glue logic.  The glue logic controls transfer direction and output enables __ Circuit Design by Jerzy R/ Chrzaszcz  Institute of Computer Science, Warsaw University of Technology, Nowowiejska, Warsaw, Poland

Power terminates DDR DRAMs -  14-Nov-02 EDN-Design Ideas - DDR (double-data-rate] SDRAMs find use in high-speed memory systems in workstations and servers.  The memory ICs operate with 1.8 or 2.5V supply voltages and require a reference voltage equal to half the supply voltage (VREF=VDD/2].  In addition, the logic outputs terminate with a resistor to the termination voltage, VTT, which equals and tracks VREF __ Circuit Design by Ron Young, Maxim Integrated Products, Sunnyvale, CA

Programming Pulse Generators for Flash Memories -  DN17 Design Notes__ Linear Technology/Analog Devices

Rolling-code generator uses flash microcontroller -  05/03/01 EDN-Design Ideas - Many security-alarm systems require the use of a random number.  A computer program uses this random number to create a sequence of random numbers to prevent unwanted visitors from gaining entry into a protected facility.  You can use a "rolling-code generator" to produce random numbers.  To implement such a generator, you would typically need a microcontroller with external memory.   __ Circuit Design by Wallace Ly

Shared-Memory Interface Eliminates Arbitration -  08/01/96 EDN-Design Ideas - The design of a shared-memory interface for the ISA bus commonly requires a relatively complex arbiter, which grants access to an onboard device or to the ISA bus.  If an on-board device requires only infrequent accesses, the circuit in Figure 1 can eliminate the need for the arbiter.  Local access occurs during the execution of an ISA refresh cycle, thereby eliminating any risk of contention.  The RFRSH line signals the beginning of the refresh cycle; as long as this signal is active, the local device has full control of the memory. __ Circuit Design by Piotr Mazur, Wikom, Warsaw, Poland

Simple Circuit FIFO provides data-width conversion -  09/26/02  EDN-Design Ideas - Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements.  However, in some applications, you need FIFO buffers for data conversion.  One example is the case in  __ Circuit Design by David Lou, Ghent University, Ghent, Belgium

Simple Circuit hookup increases AD2101's memory -  04/27/95 EDN-Design Ideas - The circuit in Fig 1 increases the memory of Analog Devices' 2101 family of fixed-point DSP µPs.  The simple scheme uses only three external static-memory devices and no glue logic.  With the additional memory, the DSP µP will have __ Circuit Design by Bogdan Morariu Digital Dispatch Systems, Richmond, BC, Canada

Simple Circuit Surface Mount Flash Memory VPP Generator -  DN58 Design Notes__ Linear Technology/Analog Devices

Strategy Processes Video In RAM -  03/18/10 EDN-Design Ideas - How you process images in RAM can eliminate problems with different image sizes.  Many video devices, such as the Analog Devices ADV7179 DAC, have analog-baseband-TV interfaces for PAL  (phase-alternating-line) and NTSC  (National Television System Committee) video signals.  Unfortunately, these kinds of DACs accept video in interlaced-image format only, but you may need progressive-scan video instead.  Furthermore, many of the progressive-scan images vary in size, which makes it more difficult to convert a progressive-scan image to an interlaced image.  Therefore, you need a universal and efficient image buffer, such as SDRAM or DRAM, as a strategy for separating the image field. __ Circuit Design by Tai-Shan Liao, National Applied Research Laboratories, Hsinchu, Taiwan


Memory Circuits


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