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 Programmable Unijunction Transistor (PUT) Circuits

Last Updated: June 02, 2021 01:44 PM

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UJT Test-  This testing procedure is for use with a digital multimeter in the OHM's test-range.  The UJT is a solid-state 3-terminal (TO-18 case) semiconductor.  UJT's are used in pulse/timing, oscillator, sensing, and thyristor triggering circuits.  The most common one being probably the 2N2646 from Motorola. __ Designed by Tony van Roon  VA3AVR

Unijunction Transistor-  The unijunction transistor (UJT) is a three terminal device with characteristics very different from the conventional 2 junction, bipolar transistor.  It is a pulse generator with the trigger or control signal applied at the emitter.  This trigger voltage is a fraction (n) of interbase voltage, Vbb.  The UJT circuit symbol, junction schematic, and characteristic curve are__ American Microsemiconductor

Verilog code Models boundary-scan TAP machin-  04/27/95 EDN Design Ideas:  Listing 1 shows a Verilog behavioral model for the Test Access Port (TAP) controller for boundary-scan test circuitry.  Boundary scan is one of the most popular methods to scan the internal nodes of a circuit.  The test circuitry for the boundary scan consists of the following: a boundary-scan register, a bypass register, an instruction register, and the TAP controller.  The principal of operation Design by Swapnajit Mittra, Wipro Infotech Ltd, Bangalore, Karnataka, India

Verilog Program Models Metastable Flip-Flop-  05/12/94 EDN Design Ideas:  The Verilog HDL program in Listing 1allows you to simulate the behavior of a set-reset (SR] flip-flop that has both its set and reset inputs high simultaneously.  The outputs of a physical SR flip-flop become indeterminate in this condition.  This property is the basis of circuits such as random-number and pseudo-noise-sequence (PSN] generators Design by Swapnajit Mittra, WIPRO Infotech Inc, Beaverton, OR

VHDL & Verilog fundamentals-  02/03/97 EDN-Design Feature To successfully design chips with Verilog or VHDL, you need to understand the basics of these hardware-description languages. Design by Douglas J Smith, VeriBest

VHDL code implements 50%-duty-cycle divider-  08/15/97 EDN Design Ideas:  Realizing a 50%-duty-cycle, divided-down clock is not always a trivial task, particularly when the divisor rate is an odd number.  You can use the VHDL source code in Listing 1 to synthesize an FPGA or a CPLD circuit that produces a 50%-duty-cycle waveform for any Design by Brian Boorman, Harris RF Communications, Rochester, NY

VHDL customizes serializer/deserializer-  06/05/00 EDN Design Ideas:  Many applications require a multiple-signal exchange among cards through a backplane.  Several solutions are available to serialize/deserialize data—from the classic UART to newer low-voltage differential-signaling components.  It is sometimes important to have hardware flexibility in transferring signals; for example, Design by Antonio Di Rocco, Siemens ICN, L’Aquila, Italy

VHDL procedure dynamically opens a file-  12/17/98 EDN Design Ideas:  (File contains many circuits.  Scroll to find this one.) A simple VHDL-87 procedure opens a file whose name a command file or user conveys in runtime.  You can apply this technique to the reading or writing of data, control, and status files.  This procedure is useful for replacing the input stimuli file of a testbench without recompiling the code (with a different stimuli file name) or rename the stimuli file name.  In addition, the procedure can write the simulation results to a file whose name consists of the input file name and any preferred extension. Design by Jacques Behar, Rockwell Semiconductor Systems, San Diego, CA

VHDL produces CRC checker-  08/03/00 EDN Design Ideas:  CRC (cyclic-redundancy checking) allows you to verify the integrity of transmitted data frames.  It finds use in many transmission protocols, both bit-oriented (High Level Data Link Control, Advanced Data Communications Control Procedure, CRC-CCITT, for example) and frame-oriented (asynchronous transfer mode, Ethernet, Fiber Distributed Data Interface, for example) Design by Antonio Di Rocco, Siemens ICN, L

Visualbasic Does I/O-  02/17/94 EDN Design Ideas:  Microsoft's VisualBasic—which runs under Windows—cannot operate on a PC's I/O ports.  However, you can add dynamic-link libraries (DLLs] to extend the keywords of native VisualBasic (Listing 1].  The compiled code, listings, and documentation in ZIPfile DI1167Z. ZIP (attached to EDN BBS /DI_SIG #1367] let you Design by Jon Titus, Test & Measurement World, Newton, MA

 Programmable Unijunction Transistor (PUT) Circuits

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