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Air Transparency Monitor, Xenon Flash Receiver - I designed this circuit many
years ago to monitor the quality of a mile long column of air for future optical
communications experiments. The transmitter system (circuit 72 below) uses a
powerful xenon flash in conjunction with a large 12 inch Fresnel lens at the
transmitter end and a matching 12-inch lens with a PIN photo diode at the
receiver. The receiver system was connected to a weather station and a computer to
collect the changes in intensity of the light flashes under different weather
conditions. It has the potential for a 30+-mile range. I have also used this
system to conduct cloud bounce experiments. ….(designed by David A. Johnson) |
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Air Transparency Monitor, Xenon Flash Receiver, Page 2 - This is Page 2 of the
receiver circuit AIR TRANSPARENCY MONITOR, XENON FLASH RECEIVER ….(designed by
David A. Johnson) |
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AN-266: Circuit Applications of Sample-Hold Amplifiers - National
Semiconductor Application Note (app note added 2/06) |
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AN-270: Applying IC Sample & Hold Amplifiers - AN-270 Analog Devices
Application Notes (app note added 6/06) |
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AN-284: Implement Infinite Sample-and-Hold Circuits using Analog Input/Output
Ports - AN-284 Analog Devices Application Notes (app note added 6/06) |
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AN-294: Special Sample & Hold Techniques - National Semiconductor Application
Note (app note added 2/06) |
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Calibrate scope jitter using a Transmission line loop - 09/20/01 EDN-Design
Ideas: Digital-clock-period jitter is variation in period of a clock
cycle compared with a nominal (average of many cycles)clock period. To accurately
measure period jitter using an oscilloscope, you must subtract oscilloscope
jitter from measured jitter. However, oscilloscopes rarely have a jitter
specification, so you must determine oscilloscope jitter.....(design idea
added 1/05) |
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Circuit Applications of Sample-Hold Amplifiers - National Semiconductor
Application Note (app note added 2/06) |
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Circuit improves on temperature measurement - 05/02/02 EDN-Design Ideas:
When current pulses with a stable IHIGH/ILOW ratio modulate a semiconductor
junction, the ensuing voltage difference (for example, ΔVBE for a bipolar
transistor)is a linear function of the absolute (Kelvin)temperature, T. You can
use this truism to make accurate temperature measurements. Technical literature
has thoroughly covered the.....(design idea added 10/03) |
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Diagnose setup & hold times in synchronous & asynchronous circuits - (Video
Design Ideas- EDN, 10/18/07) -- Metastability of digital circuits can become
a problem if you don't properly account for setup and hold times in synchronous
circuits, or at random in the case of asynchronous inputs. (electronic design idea
added 9/08) |
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Dual input sample & hold Amplifier uses no external resistors - 12/14/07 EDN-Design
Ideas: A sample-and-hold amplifier sums two inputs and holds that sum when
triggered.....(design idea added 9/08) |
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Frequency to Voltage Converter uses Sample & Hold to Improve Response & Ripple
- National Semiconductor Application Notes,28-Jun-1996 (app note added 6/06) |
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Frequency-to-Voltage Converter uses Sample-and-Hold to Improve Response & Ripple
- National Semiconductor Application Note (app note added 2/06) |
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Gain of two sample & hold Amplifier uses no external resistors - 11/08/07 EDN-Design
Ideas: If the required voltage gain of a sample-and-hold amplifier is an integer,
this circuit achieves a gain of two without using any power-dissipating external
resistors.....(design idea added 9/08) |
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Infinite Hold Circuit Zeros Out Long Term Drift - 03/03/94 EDN-Design Ideas:
The infinite-hold circuit in Fig 1 automatically zeros out long-term drift from an
instrument or a sensor. In operation, a control system (not shown)periodically
takes the instrument or sensor off line and applies a known stimulus. The known
stimulus generates a baseline-output signal.....(design idea added 3/03) |
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Inverting sample & hold Amplifier requires no external resistors - 08/02/07
EDN-Design Ideas: Eliminating external feedback resistors in an inverting
sample-and-hold amplifier allows it to exploit the full bandwidth of its op
amps.....(design idea added 09/07) |
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LB-45: Linear Brief 45 Frequency-to-Voltage Converter uses Sample-and-Hold to
Improve Response & Ripple - National Semiconductor Application Note (app
note added 2/06) |
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Low Cost Sample/ Hold Includes Two ICs - Maxim Application Notes / 19 /
Apr-07) (app note added 5/08) |
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NCO technique helps µC produce clean analog signals - 04/15/99 EDN-Design
Ideas:.....(design idea added 8/03) NCO technique helps C produce clean analog
signals. C generates musical sounds. Continuity buzzer is frugal with power.
Stereo jack adds no-cost power/logic control. S/H circuit minimizes aperture.... |
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Precision T/H Amplifier uses 3.3 Volt Supply - 06/22/95 EDN-Design Ideas:
(design idea added 3/03) |
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RF Transmitter uses AMI encoding - 11/24/99 EDN-Design Ideas: Although
alternate-mark-inversion (AMI)encoding is well-suited for direct-conversion FM
transmission, designers often overlook the technique. AMI, a three-phase,
synchronous-encoding technique, uses bipolar pulses to represent logic ones and no
signal to.....(design idea added 8/03) |
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S/H circuit minimizes aperture - 04/15/99 EDN-Design Ideas: [Note: File
contains multiple circuits. Scroll to find this one] Conventional
sample-and-hold (S/H)circuits use one hold capacitor that charges during the track
phase and disconnects during the hold phase. The voltage that the capacitor holds
usually drives an A/D converter.....(design idea added 2/06) |
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Sampling peak detector has shutdown feature - 05/16/02 EDN-Design Ideas: You
face a serious problem in using a slow ADC with a fast peak detector. The circuit
in Figure 1 allows a slow ADC to measure a fast, sampled signal peak. The 100-MHz
peak detector for ultrasonic-pulse sampling.....(design idea added 1/05) |
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Special Sample & Hold Techniques - National Semiconductor Application Note
(app note added 2/06) |
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Video Design Idea: Diagnose setup & hold times in synchronous & asynchronous
circuits - 10/18/07 EDN-Design Ideas: Metastability of digital circuits can
become a problem if you don't properly account for setup and hold times in
synchronous circuits, or at random in the case of asynchronous inputs.....(design
idea added 9/08) |