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AN-266: Circuit Applications of Sample-Hold Amplifiers: National
Semiconductor - Application Note (added 2/06) |
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AN-270: Applying IC Sample and Hold Amplifiers: AN-270 - Analog Devices Application Notes (Circuit / schematic design added
6/06) |
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AN-284: Implement Infinite Sample-and-Hold Circuits using Analog Input/Output Ports: AN-284 - Analog Devices Application Notes
(Circuit / schematic design added 6/06) |
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AN-294: Special Sample and Hold Techniques: National Semiconductor -
Application Note (added 2/06) |
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AN-775: Specifications and Architectures of Sample-and-Hold Amplifiers:
National Semiconductor - Application Note (added 2/06) |
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Calibrate scope jitter using a Transmission line loop:
09/20/01 EDN Design Ideas / (added 1/05) Digital-clock-period jitter is the variation in the period of a clock cycle
compared with a nominal (average of many cycles) clock period. To accurately measure period jitter using an oscilloscope, you must subtract
the oscilloscope jitter from the measured jitter. However, oscilloscopes rarely have a jitter specification, so you must determine the
oscilloscope jitter. ... |
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Circuit Applications of Sample-Hold Amplifiers: National Semiconductor -
Application Note (added 2/06) |
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Circuit improves on temperature measurement: 05/02/02
EDN - Design Ideas / (Electronic circuit added 10/03) When current pulses with a stable IHIGH/ILOW ratio modulate a
semiconductor junction, the ensuing voltage difference (for example, ΔVBE for a bipolar transistor) is a linear function of the absolute
(Kelvin) temperature, T. You can use this truism to make accurate temperature measurements. Technical literature has thoroughly covered the
relationship (references 1 to 4) and has numerou.... |
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Frequency to Voltage Converter uses Sample and Hold to Improve
Response and Ripple: National Semiconductor Application Notes,28-Jun-1996 (Circuit / schematic design added 6/06) |
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Frequency-to-Voltage Converter uses Sample-and-Hold to Improve Response and Ripple:
National Semiconductor - Application Note (added 2/06) |
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Infinite Hold Circuit Zeros Out Long Term Drift: 03/03/94
EDN-Design Ideas / (Electronic Circuit diagram added 03/03) The infinite-hold circuit in Fig 1 automatically zeros out long-term drift from
an instrument or a sensor. In operation, a control system (not shown) periodically takes the instrument or sensor off line and applies a known
stimulus. The known stimulus generates a baseline-output signal |
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LB-45: Linear Brief 45 Frequency-to-Voltage Converter uses Sample-and-Hold to
Improve Response and Ripple: National Semiconductor - Application Note (added 2/06) |
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Low Cost
Sample / Hold Includes Two ICs: Maxim Application Notes / 19 / Apr-07 (Circuit / schematic design added 6/06) |
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NCO technique helps µC produce clean analog signals:
04/15/99 EDN-Design Ideas / (added 8/03) NCO technique helps C produce clean analog signals. C generates musical sounds. Continuity buzzer is
frugal with power. Stereo jack adds no-cost power/logic control. S/H circuit minimizes aperture.... |
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Precision T/H Amplifier uses 33 Volt Supply: 06/22/95
EDN-Design Ideas / (Electronic Circuit diagram added 03/03) |
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RF Transmitter uses AMI encoding: 11/24/99 EDN-Design
Ideas / (added 8/03) Although alternate-mark-inversion (AMI) encoding is well-suited for direct-conversion FM transmission, designers often
overlook the technique. AMI, a three-phase, synchronous-encoding technique, uses bipolar pulses to represent logic ones and no signal to... |
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S/H circuit minimizes aperture: 04/15/99 EDN-Design Ideas
/ (added 2/06) [Note: File contains multiple circuits. Scroll to find this one] Conventional sample-and-hold (S/H) circuits
use one hold capacitor that charges during the track phase and disconnects during the hold phase. The voltage that the capacitor holds usually
drives an A/D converter that operates synchronously with the S/H control signal. This approach can sometimes place excessive demands on the
S/H circuit's bandwidth and settling capabilities. You can improve performance by using two hold capacitors to implement continuous sampling
(Figure 1). One capacitor or the other is always sampling the input signal, and the output is always the held value. A phase-reversal switch
(IC1) interconnects the input, output, and hold capacitors.... |
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Special Sample and Hold Techniques: National Semiconductor - Application
Note (added 2/06) |
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Specifications and Architectures of Sample-and-Hold Amplifiers: National
Semiconductor - Application Note (added 2/06) |
