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Sync Circuits
 

Last Updated: October 24, 2017 02:55 PM


Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

1-Gate Synchronizes Clock -  10/27/94 EDN Design Ideas:  The deceptively simple circuit in Fig 1 harbors formidable power.  Consider when you have a data-clock input to your system for an existing serial data stream.  Then, your system people surprise you __ Circuit Design by Phil Harvey, Technology Integration Inc/, Bedford, MA

2 AA cells power step-down regulator -  01/07/99 EDN Design Ideas:  (Scroll to find this one) DC/DC conversion is particularly challenging when both the input and output voltages are low.  Step-up ICs  that operate with inputs lower than 1V are available, but step-down ICs  that accept input voltages    - Page
includes several designs.   __ Circuit Design by Len Sherman, Maxim Integrated Products, Sunnyvale, CA

Digital sync-tip clamping: a new approach to video-signal conditioning -  10/08/98 EDN Design Ideas:  in digital sync-tip clamping, a stand-alone "clamping" ADC (CADC] incorporates the dc-restore function at its input and eliminates the need for external timing strobes.  This technique encompasses a complete front-end architecture, including sync detection and automatic gain control (AGC] and provide as __ Circuit Design by Lazar Shifrin, Advanced Imaging Solutions

Generating Composite Sync from Composite Video -  The circuit below illustrates generating a single positive pulse which is delayed relative to the trigger input time.  The circuit is similar to the one above but employs two stages so that both the pulse width and delay can be controlled.  When the button is depressed, the output of the first__ 

Locked-Sync Sine Generator Covers Three Decades with Low Distortion -  18-Sep-08 EDN-Design ideas This sine-wave generator can synchronize a sine-wave output through three decades of frequency and maintain low THD and constant amplitude __ Circuit Design by Alfredo H Saab and Tina Alikahi, Maxim Integrated Products, Sunnyvale, CA

LT1399/LT1399HV Triple 300MHz Current Feedback Amplifiers Drive Component Video & LCD Displays -  DN213 Design Notes__ Linear Technology/Analog Devices

Method synchronizes slaves in power-line communications -  11/09/00 EDN Design Ideas:  in PLC (power-line-communication) applications, the communications system usually uses one master and a large number of slaves (for example, 64).  The idea presented here is an easy method for the synchronization.   PDF contains multiple circuits, scroll to find the one of interest __ Circuit Design by Jose Sebastia and Diego Munoz, University of Valencia, Spain

New approach to video-signal conditioning -  10/08/98 EDN Design Ideas:  in digital sync-tip clamping, a stand-alone "clamping" ADC (CADC] incorporates the dc-restore function at its input and eliminates the need for external timing strobes.  This technique encompasses a complete front-end architecture, including sync detection and automatic gain control (AGC] and provide as __ Circuit Design by Lazar Shifrin, Advanced Imaging Solutions

Priority Encoders Slip Into FPGA -  02/17/94  EDN Design Ideas:  The standard 8-to-3 priority encoder's design, in maximal canonical form (such as the 74148) , suffers from drawbacks when you try to use the design as a macro in a large digital project.  The drawbacks are:  The number of inputs to the gates varies from two to nine; if any of the inputs develops a stuck-at-zero or stuck-at-one fault, such a fault is difficult to detect; and Reconfiguring the design to suit a fault-tolerant design is difficult.   __ Circuit Design by Swapnajit Mittra, Baharat Electronics, Bangalore, India

Single Gate Synchronizes Clock -  10/27/94 EDN Design Ideas:  The deceptively simple circuit in Fig 1 harbors formidable power.  Consider when you have a data-clock input to your system for an existing serial data stream.  Then, your system people surprise you __ Circuit Design by Phil Harvey, Technology Integration Inc/, Bedford, MA

Solid-State Relay Saves Battery's Life -  09/01/94 EDN Design Ideas:  The circuit in Fig 1 uses a low-resistance p-channel FET, Q4, to disconnect a load from the battery when the battery's voltage drops below a certain value.  After you disconnect the circuit, it remains off until you remove and replace the battery __ Circuit Design by Tom Gay, Siemens, Regensburg, Germany

Sync Separator Includes AGC -  05/11/95 EDN Design Ideas:  This sync separation circuit has a gain-control circuit that helps to stabilize the sync-separation function __ Circuit Design by Dana Romero, Salt Lake City, UT-- 05/11/95

Synchronize asynchronous reset -  01/06/00 EDN Design Ideas:  Synchronous reset and asynchronous reset are both common reset mechanisms for state machines, and the reset circuit in Figure 1 combines the advantages of each.  Synchronous reset has the advantage of synchronization between clock and reset signals, which prevents race conditions from occurring between the clock and the reset signal.  However,  __ Circuit Design by Willy Tjanaka

Synchronized Regulator Produces Coherent Noise -  03/17/94 EDN Design Ideas:  By using a gated-oscillator architecture instead of a clocked-PWM one, gated-oscillator-type switching regulators permit high efficiency over extended ranges of output current.  This architecture eliminates the housekeeping currents associated with the continuous operation of fixed-frequency designs.  Gated-oscillator regulators simply self-clock at whatever frequency is necessary to maintain the output voltage.  Typically, loop-oscillation frequency ranges from a few hertz to the kilohertz region, depending on the load.    __ Circuit Design by Jim Williams, Sean Gold, and Steve Pietkiewicz, Linear Technology, Milpitas, CA

Synchronized Timing Generators  -  Circuit ideas for Designers App Note__ Advanced Linear Devices, Inc

Synchronized Window Comparator Eliminates Error -  05/11/95 EDN Design Ideas:  Precision A/D converters need a window comparator.  The window comparator in Fig 1a is synchronized to the clock signal.  This synchronization eliminates errors that could arise when the input signal crosses the high or low threshold (Fig 1b]unsynchronized to clock.  in operation, comparator IC 1A sets flip-flop IC 2 __ Circuit Design by Sergey Velichko, Consultant, Bosie, ID

Synchronizing Controller Detects baud rate -  03/02/98 EDN Design Ideas:  NOTE:  File contains many circuits, please scroll to find this one.  A simple and inexpensive implementation using an eight-pin 12C508 controller (Microchip Technology, Chandler, AZ] provide as both bit-rate detection and a synchronous, appended-clock output from an asynchronous input-data stream (Figure 1a].    __ Circuit Design by William Grill, Riverhead Systems, Littleton, CO

Synchronous Buck Produces Negative Voltage -  6-Mar-03 EDN Design Ideas:  Many electronic systems require both positive and negative voltages to operate properly.  Generating an efficient, low-voltage positive output from a higher voltage input typically entails the use of a synchronous buck regulator.  But when generating a negative output voltage from a positive input voltage, you'd typically use a flyback topology, especially at higher output currents __ Circuit Design by John Betten, Texas Instruments, Dallas, TX

Synchronous flyback provides high-efficiency conversion -  07/22/04 EDN Design Ideas:  Buck regulators are usually the first choice when you design nonisolated step-down regulators unless the ratio of ViN to VOUT is greater than 10, the input voltage is high, or both.  Low duty cycle can be problematic for FET drivers and cause current-mode control loops to lose control.  Efficiency can fall dramatically to 60 to 70% at low VOUT and current of only a few amps __ Circuit Design by Wayne Rewinkel, National Semiconductor, Phoenix, AZ

Synchronous Oscillator Converts Audio, Video to FM  -  07/22/99 EDN Design Ideas:  The synchronous oscillator (SO) and the coherent phase-locked synchronous oscillator (CPSO) are universal multifunctional networks that track, synchronize, and amplify as much as 80 dB; improve SNR by as much as 70 dB; and modulate AM, FM, and FSK signals __ Circuit Design by Vasil Uzunoglu, Synchtrack, Gaithersburg, MD

Synthesize optimal digital-frequency dividers -  05/13/99 EDN Design Ideas:  For many applications, you need to divide a reference clock into one or more subclocks to use in different parts of the system.  Sometimes, PDF contains many circuits, scroll to find this one.    __ Circuit Design by Lindo St Angel, PrairieComm Inc, Arlington Heights, IL

TV/Radio Antenna Cable galvanic isolator -  A ground loop in your AV system caused by antenna connection or TV cable is very common if you have your computer connected to the same system.  This type of ground loop problem can be solved by using suitable isolation between your AV system and the antenna cable.  The simplest way to get rid of the hum is to disconnect the antenna cable from the AV system.  if you still want to watch cabe TV or listen to your radio an keep the system hum free then you have to install isolators to all those antenna cable connections your system has __ Designed by Tomi Engdahl

Two AA cells power step-down regulator -  01/07/99 EDN Design Ideas:  (Scroll to find this one) DC/DC conversion is particularly challenging when both the input and output voltages are low.  Step-up ICs  that operate with inputs lower than 1V are available, but step-down ICs  that accept input voltages    - Page
includes several designs.   __ Circuit Design by Len Sherman, Maxim Integrated Products, Sunnyvale, CA

Video Difference Amplifier Brings Versatility to Low Voltage Applications -  DN343 Design Notes__ Linear Technology/Analog Devices

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Sync Circuits

 


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