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Delay Circuits
Delay Circuits: #'s - H
I - Z
Last Updated on:
Friday, October 16, 2009 03:41 AM |
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Circuits Designed by Dave Johnson, P.E. : |
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LONG PERIOD COMPUTER WATCH DOG TIMER
This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a
computer. Should the computer fail to send a pulse, the
output changes state. The time can easily be set from seconds to hours.
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Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
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Butterworth Filter has Adjustable Group Delay - 08/08/02 EDN Design Ideas /
(added 1/05)The Sallen-Key realization of a 5.25-MHz, three-pole Butterworth filter
has a gain of 2V/V and can drive 75Ω back-terminated coax with an overall gain of 1
(Figure 1). Used to reconstruct component-video (Y, Pb, Pr) and RGB signals, this
filter has an insertion loss greater than 20 db at 13.5 MHz and greater than 40 db at
27 MHz (Figure 2).... |
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Delay Line Aids in One Shot Simulations - 02/05/2004 EDN-Design Ideas In
low-noise analog circuits, a high-gain amplifier serves at the input to increase the
SNR. The input signal level determines the input-stage gain; low-level signals require
the highest gain. It is also standard practice in low-noise analog-signal processing
to make the circuit's bandwidth as narrow as possible to pass only the useful
input-signal spectrum. (added 10/05) |
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Delay Line Eases SPICE Dead Time Generation - (Design Ideas - EDN, 03/02/2000)
Generating complementary clock signals in a Spice simulation is an easy task. However,
this task gets much harder if you need to introduce some dead time into the signals.
This difficulty is especially true when you're dealing with a
variable-pulse-width-modulated switching cycle. (electronic design idea added 10/05)
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Delay Line has Wide Duty Cycle Range - 06/27/02 EDN Design Ideas / (added
1/05)Today's digital delay lines can process pulses no shorter than their delay times,
and that restriction confines the devices to applications in which the duty cycle
remains near 50%. A limited range of available delays (2 to 100 nsec per tap) further
limits their use. Longer delay is available with one-shot multivibrators of standard
digital-logic families, but those devices do not retain duty-c...... |
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Delay Line Implements Clock Doubler - (07/18/96 EDN-Design Ideas / (added 3/03) |
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Delay Line Upgrades Vintage Scope - 04/18/02 EDN Design Ideas / (added 1/05)
Vintage triggered-sweep oscilloscopes find use in many applications. However, they
have no internal delay line, so they can't display the pulse that triggers the sweep.
Moreover, early laboratory scopes contain delay lines having insufficient delay to
display such pulses during a uniform portion of the sweep.... |
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Delay Simulator Debugs Communications Equipment - 10/27/94 EDN Design Ideas /
(added 08/05) Phone calls over satellite circuits experience a ¼-sec transmission
delay in each direction. The low-cost circuit (around $20) in Fig 1a simulates this
delay and provides hooks for inserting noise, echo, and other impairments. Designers
debugging modems, fax machines, and other communication equipment can use this circuit
to troubleshoot .... |
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Delayed DC Power - This circuit Creates a Tiny Power Delay to a Circuit. Read Why
I designed it....(circuit design added 12/08) |
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Delayed Interface to Kodak DC-20 Camera - designed by Jon Fick (electronic circuit
added 05/06) |
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Delayed Off Light Switch - This is an unusual design in that it uses plain metal
gate CMOS logic instead of the usual PIC or a custom chip. The 22uF capacitor charges
up during one half of the ac cycle, and supplies trigger current to the triac on both
halves. (added 2/05) |
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Delayed Shutter Control for Kodak DC-20 - (circuit / schematic design added 6/06) |
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Feedback Circuit Eliminates CCD Driver Delay Mismatch - 09/18/03 EDN Design
Ideas / (added 1/05) In a CCD (charge-coupled device), packets of charges shift
across the array. The transistor array, also called a bucket-brigade shift
register, receives drive from a dual-phase clock signal. Dual-phase clock signals
comprise two synchronized clock signals that are 180° out of phase. High
peak-output-current CCD drivers can buffer the logic-level ..... |
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Generating a Delayed Pulse With a dual 555 Timer - The circuit below
illustrates generating a single positive pulse which is delayed relative to the
trigger input time. The circuit is similar to the one above but employs two stages
so that both the pulse width and delay can be controlled. When the button is
depressed, the output of the first....(schematic / circuit added 2/07) |
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Generating Long Time Delays - Generating long delays of several hours can be
accomplished by using a low frequency oscillator and a binary counter as shown
below. A single Schmitt Trigger inverter stage (1/6 of 74HC14) is used as a
squarewave oscillator to produce a low frequency of about 0.5 Hertz. The 10K
resistor in series with the input (pin 1) reduces the capacitor discharge current
through...(circuit / schematic design added 6/06) |
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Generating Long Time Delays circuitdb - Generating long delays of several
hours can be accomplished by using a low frequency oscillator and a binary counter
as shown below. A single Schmitt Trigger inverter stage (1/6 of 74HC14) is used
as.... (added 2/07) |
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Group Delay Equalizer has Gain More Than One - 10/12/95 EDN-Design Ideas /
(added 6/06) |
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High And Low Voltage Cut Off With Time Delay - The power line fluctuations and
cut-offs cause damages to electrical appliances connected to the line. It is more
serious in the case of domestic appliances like fridge and air conditioners. If a
fridge is operated on low voltage, excessive current flows through the motor,
which heats up, and get damaged.….(electronic schematic added 08/08) |
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Delay Circuits:
#'s - H I - Z |
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