Phase Locked Loop Based Clock Generators:  National Semiconductor Application Note 04-Nov-1995 (Electronic Schematic / circuit added 4/02)

Phase locked loop fundamentals:  Application Note - MiniCircuits.com  (Circuit / schematic design added 6/06)

Phase Locked Loop IC as a Communication System Building Block:  National Semiconductor Application Note 04-Nov-1995 (Electronic Schematic / circuit added 4/02)

Phased Lock Loop Schematic:  (Electronic circuit added 7/03)

Phase-Locked Loop Based Clock Generators:  National Semiconductor - Application Note   (added 2/06)

PLL FM Transmitter:  (added 2/06)

PLL forms simple MSK demodulator :  12/17/98 EDN-Design Ideas  / (added 2/06)   In minimum-shift-keying (MSK) signaling, two frequencies that differ by the bit rate represent a one bit and a zero bit. Normally, the frequency shift occurs at the peak of a cycle, so that neither the amplitude nor the slope of the waveform shows a discontinuity. We needed to transmit 300-baud ASCII text using ultrasonic transducers. These devices have a very narrow bandwidth around their 25-kHz resonant frequency, making MSK the obvious choice for modulation. A zero bit becomes 84 cycles of 25.2 kHz, and a one bit is 83 cycles of 24.9 kHz. It is easy to generate this signal with a PIC µC and an 8-bit DAC. However, a traditional MSK demodulator circuit uses a center-frequency VCO and several mixers and filters. This design needs something simpler: to wit, the circuit in Figure 1....

PLL IC forms simple digital phase shifter:  01/04/96 EDN-Design Ideas / (added 2/06)

PLL implements FPGA based SDRAM Controller :  05/21/98 EDN-Design Ideas / (added 2/06)  As FPGA capabilities increase and time to market decreases, FPGAs gain more acceptance for implementing both data and control paths. Thus, they find wide use as controllers and datapath glue logic for fast-page DRAMs. Synchronous DRAMs (SDRAMs), whose control signals use a clock input as reference, are a natural target for FPGA-based controllers. SDRAMs operate at frequencies of 100 MHz and higher (in contrast with fast-page DRAMs, for which a 60-MHz memory-system clock was considered high). Figure 1 shows a way to implement FPGA-based SDRAM controllers. Figure 2 shows the timing for a Xilinx XC4010E-2 device. You can apply the method to FPGAs from other vendors, as well as to high-frequency systems other than SDRAMs.... 

PLL Jitter and Its Effects in the CAN Protocol:  Microchip Application Note - Published 15-Jun-04   (added 2/06)

PLL synchronizes power-supply IC :  07/16/98 EDN-Design Ideas  / (added 2/06)

PLL Synthesizing Oscillator (1):  (Electronic circuit added 7/03)

PLL Synthesizing Oscillator (2):  (Electronic circuit added 7/03)

PLL Synthesizing Oscillator (3):  (Electronic circuit added 7/03)

PLL Tutorial:  (added 2/06)

PLL-based converter controls light source :  07/02/98 EDN-Design Ideas  / (added 2/06)   Using the circuit in Figure 1, you can digitally control the light intensity of a lamp. The control loop is based on a PLL, in which the VCO comprises a light-to-frequency converter (TSL220) coupled to a light source that derives its drive from a switching regulator (L4970A). The output of the phase/frequency comparator (4046) serves as the control voltage for the switching regulator. The control voltage is proportional to the frequency error between the reference frequency (fREF) and the signal frequency (fIN) coming from the light-to-frequency converter. Changing the reference frequency regulates the voltage supplied to the lamp to force the output of the TSL220 to lock to fREF. The two resistors at the output of the 4046 provide an attenuation of 1000 to guarantee the loop stability....

Precautions for Disk Data Separator   (PLL) Designs:  National Semiconductor - Application Note   (added 2/06)