Add a Schmitt trigger function to CPLDs FPGAs and applications:  10/13/05 EDN Design Ideas  / (added 11/05)  For slow-slewing signals, hysteresis solves trigger problem.

Changes Improve Schmitt Trigger:  05/13/99 EDN-Design Ideas / (added 11/05)

Contact debouncing algorithm emulates Schmitt trigger:  07/07/05 EDN Design Ideas  / (Circuit / schematic design added 6/06)  Another approach to solving the ubiquitous contact debounce problem.

DPP adds versatility to VFC:  11/14/02 EDN Design Ideas  /  (added 1/05)  The basic VFC (voltage-to-frequency converter) in Figure 1 comprises an integrator (IC1) and a Schmitt-trigger circuit (IC2). The integrator converts the dc input voltage, VIN , to a linear voltage ramp, and the Schmitt trigger sets the limits of the integrator's output voltage. Feedback around both circuits provides the condition for oscillation....

Oscillator Extends Schmitt Triggers' Reach:  01/19/95 EDN-Design Ideas / (Electronic Circuit diagram added 03/03)

Resistor network extends Schmitt trigger's reach:  09/13/01 EDN Design Ideas  /  (added 1/05)  The circuit in Figure 1 shows a familiar technique for converting a low-level analog signal to digital form. Resistors R1 and R2 set the quiescent dc level at the Schmitt inverter's input to a value roughly equal to the midpoint of the hysteresis band. Capacitor C1 removes dc content from VIN, such that the Schmitt trigger's input signal, VI, centers itself on the midhysteresis level. ...

SC (Schmitt Comparator) Head:  A simple little design by Martin Keen and Wilf Rigter  (Circuit / schematic design added 6/06)

Schmitt Trigger has Dynamic threshold:  06/05/97 EDN-Design Ideas / (Electronic Circuit diagram added 03/03)  

Simple changes improve Schmitt trigger:  05/13/99 EDN-Design Ideas / (added 11/05)

Transistor Schmitt Trigger Oscillator:  The Schmitt Trigger oscillator below employs 3 transistors, 6 resistors and a capacitor to generate a square waveform. Pulse waveforms can be generated with an additional diode and resistor (R6). Q1 and Q2 are connected with a common emitter resistor (R1) so that the conduction of one transistor causes the other to turn off. Q3 is controlled by Q2 and provides the squarewave output from the collector. In operation, the timing capacitor charges and discharges through the feedback resistor (Rf) toward the output voltage. When the capacitor voltage rises above the base voltage at Q2, Q1 begins to conduct, causing Q2 and Q3 to turn off, and the output voltage to fall to 0. This in turn produces a lower voltage at the base of Q2 and causes the capacitor...   (Circuit / schematic design added 6/06)