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Backup Clock Controller Checks Time Setting: 01/05/95 EDN-Design Ideas /
(added 3/03) |
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Basic 555 Monostable: (circuit / schematic design added 6/06) |
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Bedside Lamp timer: (circuit added 9/04) |
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Big LED Clock: (circuit / schematic added 5/03) |
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Binary Counter uses LSB Feedforward: 08/05/99 EDN Design Ideas / (added
09/05) A typical synchronous binary counter contains a series of flip-flops, each of
which changes state when all least significant bits (LSBs) are logic 1. This repeated
AND function is Achilles' heel of binary counter. A designer has two
choices: Use a ripple AND function (Figure 1), or a parallel AND function (Figure
2).... |
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Bistable Switch: This circuit shows how to implement a simple bistable
(On/Off) switch. You can also do this with a Schmitt trigger gate or inverter. Just
set R1 and R2 to bias input to center point of Schmitt trigger’s
hysteresis.
Designed by Andrew
R. Morris
(added 09/05) |
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Bootstrapped Timer: This circuit demonstrates how to use bootstrapping to
seriously boost output power of timer. The LC555 can only put out about
50mA as it is. This circuit can put out at least 200mA and goes to rail as well.
The LM555 timer puts out 300mA max, but doesn’t go all way to rail.
Replace Q1 with a big MOSFET, and you can put out big current with se few components.
Designed by Andrew
R. Morris
(added 09/05) |
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Budget timer: (schematic added 8/03) |
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Build a simple one chip phototimer: 07)/08/04 EDN Design Ideas /
(added 1/05) The author of this Design Idea needed to
automatically switch on a lamp when it became dark and keep it on for a given time. He
couldn't find an inexpensive device that satisfied requirement. So he designed a
phototimer from scratch based on low-end, eight-pin flash microcontroller
MC68HC908QT2 from Motorola. |
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CA4060B Timer Circuits: (diagram added 05/07) |
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Cheap 40KHz Clock: (schematic added 8/03) |
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Choose termination and topology to maximize signal integrity and timing:
10/24/96 EDN-Design Feature / (added 2/06) Termination techniques improve noise
margins and reduce signal reflections, but they require that you balance trade-offs
among conflicting goals. Understanding your choices and their design impact helps you
produce a more reliable and cost-effective design.—Mai Vu, Harris Computer Systems
Corp |
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Circuit Allows high speed clock multiplication: 05/02/02 EDN Design Ideas
/ (added 1/05) In theory, synchronous clock multiplication is an easy
task. A simple PLL with two digital dividers—one inserted just after the VCO
(voltage-controlled oscillator) and the second one placed directly at the input of the
phase detector—may do the job. The flexibility of such a configuration allows for
clock multiplication by any rational number.... |
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Circuit Avoids Metastability: 08/30/01 EDN Design Ideas(added 02/05)
Consider a computer system that has a host processor connected to a remote-I/O
subsystem (Figure 1). The host clock treats the I/O system, which is located far from
the main hardware, as a slave. Because of the transmitters, receivers, remote-system
logic, and cable length, the data the host receives has a dramatic latency. ... |
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Circuit Conditions Variable Duty Cycle Clock: 02/17/97 EDN-Design Ideas /
(added 11/05) The circuit accepts an input clock of any duty cycle and generates any
desired duty cycle at the output. You need to add only one flip-flop to the earlier
design to generate an arbitrary-duty-cycle output. You can use the circuit to correct
a non-50% input to a 50% output or to create a non-50% output from any arbitrary input
duty cycle..... |
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Circuit Converts Solid State Relay to Timer: 05/09/96 EDN-Design Ideas /
(added 2/03) |
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Circuit Counts Logic ones on Signal Lines: 02/01/96 EDN-Design Ideas /
(added 3/03) |
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Circuit divides frequency by N+1: 07)/11/02 EDN Design Ideas /
(added 1/05) Digital frequency dividers usually use flip-flop stages that
connect the Q pin to the D data-input pin of the following stage. This configuration
creates a binary waveform that you can feed back to the input. You can divide any
integer lower than 2N with minimal stages, where N is the number of stages.... |
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Circuit Emulates Mechanical Metronome: 08/19/99 EDN-Design Ideas / (added
4/05)) produces Timing signals with a sound like that of a mechanical metronome. IC1
is a555 Timer that oscillates at approximately3200 Hz. The two3-kW resistors and
the0.047-µF capacitor set the frequency. IC2 divides the frequency of IC1s output by2.
IC2 produces a square wave with an exact50% duty cycle. |
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Circuit provides linear resistance to time conversion: 08/07)/03 EDN Design
Ideas / (added 1/05) Resistance-based transducers, such as strain
gauges and piezoresistive devices, find common use in the measurement of several
physical parameters. For applications in which digital processors or microcontrollers
serve for data acquisition and signal processing, the transducer's response must
assume a form suitable for conversion to digital format.... |
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Circuit Provides Serial or Sequential Timing: 09/26/96 EDN-Design Ideas /
(added 3/03) |
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Circuit Provides Timebase Calibration: 04/24/97 EDN-Design Ideas / (added
3/03) |
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Circuit provides Watchdog for microControllers: 12/26/02 EDN Design Ideas
/ (added 1/05) The watchdog circuit in Figure 1 uses a single NAND
Schmitt-trigger IC. The circuit is more cost-effective than dedicated, commercially
available watchdog ICs. The circuit generates an active-high reset signal upon
power-up and remains in a low state as long as the control input receives pulses.
Whenever the pulsing at the control input stops, whether the circuit is in a high or a
low state, th...... |
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Circuit Provides Watchdog for Microcontrollers: 12/26/02 EDN Design Ideas
/ (added 1/05) The watchdog circuit in Figure 1 uses a single NAND
Schmitt-trigger IC. The circuit is more cost-effective than dedicated, commercially
available watchdog ICs. The circuit generates an active-high reset signal upon
power-up and remains in a low state as long as the control input receives pulses.
Whenever the pulsing at the control input stops, whether the circuit is in a high or a
low state, th...... |
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Circuit Times Bathroom Fan: 04/27/00 EDN-Design Ideas / (added 11/05)
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Clock Basics: Pericom Semiconductor Application Brief # 037 (app note added
02/05) |
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Clock Divider Circuit: (electronic Circuit diagram added 03/03) |
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Clock divider: (circuit added 05/07) |
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Clock Divider: 02/17/97 EDN-Design Ideas / (added 11/05) The circuit accepts
an input clock of any duty cycle and generates any desired duty cycle at the output.
You need to add only one flip-flop to the earlier design to generate an
arbitrary-duty-cycle output. You can use the circuit to correct a non-50% input to a
50% output or to create a non-50% output from any .... |
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Clock Doubler for CMOS Logic: (circuit added 7/02) |
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Clock doubler: (electronic schematic added 05/07) |
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Clock Fail Circuit Switches to Alternate Clock: 10/24/96 EDN-Design Ideas /
(added 3/03) |
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Clock Generator: Use4093 oscillator (added 4/02) |
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Clock Performance in RAID Storage Applications: PI6C2502: Pericom
Semiconductor Application Note # 026 (app note added 02/05) |
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Clock Recovery PLL Fits into Single PLD: 11/23/95 EDN-Design Ideas / (added
2/06) |
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Clock Solutions for WIFI (IEEE 802.11): Pericom Semiconductor Application
Note # 07)0 (app note added 02/05) |
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Clock Switching Circuit Banishes Glitches: 12/19/96 EDN-Design Ideas / (added
3/03) |
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Clock Termination Techniques: Pericom Semiconductor Application Brief # 023
(app note added 02/05) |
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CMOS oscillator: (electronic circuit added 05/07) |
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Computerised Universal Timer: (electronic Circuit / Schematic added 10/04) |
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Constant on Time Buck/Boost Regulator Converts a Positive Input to a Negative Output:
12/07)/04 EDN Design Ideas / (added 6/06) Buck regulators find wide
application as step-down regulators for converting large positive input voltages into
a smaller positive output voltages. Figure 1 shows a simplified buck regulator that
operates in continuous-conduction mode—that is, the inductor current always remains
positive. The output voltage, VOUT, is equal to D×VIN, where D is the duty-cycle ratio
of the buck switc... |
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Control a Processor's Power Supply in Real Time: 03/31/05 EDN Design Ideas
/ (added 6/06) Dynamic control of processor's supply rail minimizes power
consumption. |
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Countdown timer with Relay: (schematic added 8/03) |
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Counter IC Provides Wait States for 8031/8051: 06/22/95 EDN-Design Ideas /
(added 3/03) |
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Counting Events using 16-bit Timer: Toshiba 900H Series Application Note
(app note added 2/06) |
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Courtesy Lamp: 15 seconds delayed switch-off for220-Volt AC lamp, a good
idea for bedroom lamps (added 9/04) |
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Crosstalk on the Clock (Part 2): Maxim Application Notes / 1841 / Nov-04
(app note added 6/06) |
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Crystal 32.768KHz CMOS Oscillator: (diagram added 05/07) |
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Crystal oscillator: (electronic circuit added 05/07) |
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Crystal-Controlled Time-Base Generator: (electronic Circuit / Schematic
added 10/04) |
