Timers and Counters Electronic Circuits, page 3

Timers and Counters Circuits, Page 3
Timers & Counters: #-A B-E Next F-L M-S T-Z
Last Updated on: Friday, March 12, 2010 12:07 PM

Circuits Designed by Dave Johnson, P.E. :

HONEYBEE COUNTER
I designed a circuit similar to this one a long time ago to help a beekeeper count the number of bees going into or out of a hive. The low power circuit uses a slotted opto-sensor to detect the passing bees. The circuit advances an electronic counting module whenever a honeybee passes through the sensor. The device only counts the number of bees going through the sensor. A different circuit would be needed to count the number of bees only going out or only coming into the hive.

LONG PERIOD COMPUTER WATCH DOG TIMER
This circuit uses a simple 4060 IC oscillator/timer which is reset periodically by a computer. Should the computer fail to send a pulse, the output changes state. The time can easily be set from seconds to hours.

Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

Failed Power Light: turns on small low voltage lighting when mains power disappears (added 4/02)

Fan timer Based on Motorola 68HC908QT2: (circuit / schematic added 6/05)

Frequency counter: (circuit / schematic added 6/05)

Frequently Asked Questions on DDR Applications: Pericom Semiconductor App Note # 027 (app note added 02/05)

Fundamentals of Modal Testing: Aligent App Note (added 2/06)

Galloping Neon: array of blinking neon lamps (added 8/03)

Gated clock has duty-cycle control: 08/17/00 EDN-Design Ideas / (added 2/06) The circuit in Figure 1 produces clock pulses with variable duty cycle from a gated clock. The output of the circuit, pulse, is always 180° out of phase with the clock input. When the delay-logic elements, IC5 and IC7, have the same propagation delays, the duty cycle of the circuit's output is 50%. The circuit produces gated clock pulses when the gate input, gate, is high and the active-low reset, reset_n, is high. Increasing the propagation delays of the increase-duty-cycle delay-logic element, IC5, causes an increase in the duty cycle of the gated-clock output, pulse. The decrease-duty-cycle delay-logic element, IC7, reduces the duty cycle of the gated-clock output. Listing 1 is a Verilog model of the circuit;

General Routing Techniques with Emphasis on PI6C10X Clocks: Pericom Semiconductor Application Note # 008 (app note added 02/05)

Generating a Delayed Pulse with a Dual 555 Timer: (schematic added 8/03)

Generating Interrupts at Regular Intervals using 16-bit Timer: Toshiba 900H Series Application Note (app note added 2/06)

Generating Long Time Delays (circuitdb): Generating long delays of several hours can be accomplished by using a low frequency oscillator and a binary counter as shown below. A single Schmitt Trigger inverter stage (1/6 of 74HC14) is used as a squarewave oscillator to produce a low frequency of about 0.5 Hertz..... (added 05/07)

Generating Long Time Delays: (electronic circuit added 10/05)

Generating Multiple Clock Outputs from the AD9540: AN-769 Analog Devices Application Notes (app note added 2/06)

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