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Car Tachometer - A 555 is configured as a monostable or one shot in this project. The period of the 555 is determined by the 47k and the capacitor from pin 6 to ground (100n). Time "T" = 1.1 RCor1.1 X 50, 000 X 0.1X10 -6=0.0055 or 5.5 mS (milli-seconds) __ 555-Timer
Car timer power controller AtTiny45 - Automotive, car and motorcycle electronic circuit diagrams / circuit schematics __ Designed by Thomas Scherrer OZ2CPU
Cascade Two Decade Counters to Obtain 19-Step Sequential Counter - 14-Dec-07 EDN Design Ideas: interleaving the outputs of a pair of Johnson counters yields a 19-step, sequential count Design by Jeff Tregre, Dallas, TX
Ceiling Fan Timer - it runs the fan in your bathroom or toilet for a fixed time after you turn it on and has two modes of operation__ SiliconChip
Cell Phone Detector aka Mobile Bug - This handy mobile bug or cell phone detector, pocket-size mobile transmission detector or sniffer can sense the presence of an activated mobile cellphone from a distance of one and-a-half metres. So it can be used to prevent use of mobile phones in examination halls, confidential rooms, etc. it is also useful for detecting the __ Designed by Popescu Marian
Chicken Coop Door Opener with Timer - I received an email from a guy in Australia who was trying to build a chicken coop system. He was planning on using a conventional garage door mechanism to open and close the 6 doors to the coop. The commercial door opener opened and closed the doors with a single pushbutton. He wanted to install a standard 220vac powered timer so he could open the doors in the morning and close them at night. . . Circuit by Dave Johnson P.E.-March, 2013
Choose termination & topology to maximize Signal integrity & timing - 10/24/96 EDN-Design Feature Termination techniques improve noise margins and reduce signal reflections, but they require that you balance trade-offs among conflicting goals. Understanding your choices and their design impact helps you produce a more reliable and cost-effective design Design by —Mai Vu, Harris Computer Systems Corp
Christmas Decoration - This project flashes 18 LEDs at three different rates and you can use these to create a Christmas decoration of your choice. The circuit is kept simple (and cheap!) by using the 4060B IC which is a counter and oscillator (clock) in one package. The circuit requires a 9V supply, such as a PP3 battery __ Designed by John Hewes
Circuit allows high-speed clock multiplication - 05/02/02 EDN Design Ideas: in theory, synchronous clock multiplication is an easy task. A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator] and the second one placed directly at the input of the phase detector—may do the job. The flexibility of such a configuration allows for clock multiplication by any rational number Design by Lukasz Sliwczynski and Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow, Poland
Circuit avoids metastability - 08/30/01 EDN Design Ideas: Consider a computer system that has a host processor connected to a remote-i/O subsystem (Figure 1). The host clock treats the i/O system, which is located far from the main hardware, as a slave. Because of the transmitters, receive Design by Jonathan Eckrich, Adaptivation, Sioux Falls, SD
Circuit conditions variable-duty-cycle clock - 02/17/97 EDN Design Ideas: Simple enhancement of an earlier Design idea ("Delay line implements clock doubler", EDN, July 18, 1996, pg 102) implements a variable-duty-cycle clock-signal conditioner. The circuit accepts an input clock of any duty cycle and generates any desired duty cycle at the output. You need to add only one flip-flop to the earlier design to generate an arbitrary-duty-cycle output. You can use the circuit to correct a non-50% input to a 50% output or to create a non-50% output from any arbitrary input duty cycle Design by David Albean, Thomson Consumer Electronics, Indianapolis, IN
Circuit Converts Solid-state Relay to Timer - 05/09/96 EDN Design Ideas: Finding a 480V-ac solid-state timer having zero-crossover switching may prove to be an impossible task. Most solid-state timers are rated at only 1A and have voltage ratings no higher than 240V ac. Solid-state relays (SSRs) , in co Design by Henno Normet, Tavares, FL
Circuit counts logic ones on signal lines - 02/01/96 EDN Design Ideas: in some cases, you may need to monitor the number of logic ones present on a set of signal lines. in the classic method to provide this monitoring function, the parallel-counter circuit that Reference 1 describes counts the number of ones on a set of N-1 signal lines, where N is a power of two Design by Robert Inkol Defense Research Establishment Ottawa, ON, Canada
Circuit divides frequency by N+1 - 07/11/02 EDN Design Ideas: Digital frequency dividers usually use flip-flop stages that connect the Q pin to the D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to the input. You can divide any integer lower than 2N with minimal stages, where N is the number of stages Design by Bert Erickson, Fayetteville, NY
Circuit Emulates Mechanical Metronome - 08/19/99 EDN Design Ideas: The circuit in Figure 1 produces timing signals with a sound like that of a mechanical metronome. IC 1 is a 555 timer that oscillates at approximately 3200 Hz. The two 3-kW resistors and the 0.047-µF capacitor set the frequency. IC 2 divideas the frequency of IC 1 's output by 2. IC 2 produces a square wave with an exact 50% duty cycle. Design by Jim Kocsis
Circuit Forms Divide By 1.5 Counter - Two inexpensive ICs divide a TTL clock signal by 1.5. By following the circuit with another flip/flop, you could also generate a divide by three function. . . Circuit by Dave Johnson P.E.-July, 2000
Circuit gates pulse train without truncating - EDN Design Ideas: Jan 12, 2015 To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task. in most cases, a simple AND gate will cause problems, see Figure 1. Clock pulses pass through the AND gate as long as the asynchronous strobe E is high. if loss or distortion of even one pulse is critical, then the simple AND gate is unsuitable, as the first and the last pulse in the burst will often be distorted (shorter than usual pulse) due to the lack of synchronization between clock and E. Design by Viktor Safronov
Circuit Improves On Earlier Idea - EDN Design Ideas: 05/24/2012 A self-biasing thermistor circuit had an overall dominant thermal/electrical time constant as small as 25 msec but had a significantly rounded response following a square (thermal) input pulse of 100 msec; the source was a pulsed blue LED. A single-op-amp-based “anticipator-like” circuit generated a more faithful picture of the actual input excitation, and improved on the circuit described in a previous Design ideas (Reference 1). The lowpass filter in Figure 1, with an RC time constant of approximately 25 msec, models the circuit. Design by Nicholas Lockerbie, Scottish Universities Physics Alliance, Glasgow, Scotland
Circuit Provides Linear Resistance-To-Time Conversion - 7-Aug-03 EDN Design Ideas: Resistance-based transducers, such as strain gauges and piezoresistive devices, find common use in the measurement of several physical parameters. For applications in which digital processors or microcontrollers serve for data acquisition and signal processing, the transducer's response must assume a form suitable for conversion to digital format Design by
Kaliyugavaradan and D Arul Raj, Anna University, Chennai, India
Circuit provides serial or sequential timing - EDN Design ideas - 09/26/1996 The circuit in Figure 1 gives an application for an earlier Design idea (Reference 1). in this design, you can adjust as many as eight time intervals, and repeated operation is optional. You can use the timer to control the external load either serially or sequentially, depending on the application. The basic timer uses a 4060 (IC 4) with a fixed timing capacitor. The analog switches connect the timing resistors to the circuit. A five-stage Johnson counter, IC 1, controls the analog switches. Design by Sanjay R Chendvankar, Tata Institute of Fundamental Research, Bombay, India
Circuit Provides Timebase Calibration - 04/24/97 EDN Design Ideas: The circuit in Figure 1 provide as an inexpensive and quick way to check the timebase speeds and linearity in vintage oscilloscopes. Component aging in the oscilloscopes sometimes alters the timebase parameters enough to yield grossly erroneous results. You can make timing adjustments in the oscilloscope by using the timing waveforms from the circuit in Figure 1 Design by William Whitehead, Lafayette, CO
Circuit provides watchdog for microcontrollers - 12/26/02 EDN Design Ideas: The watchdog circuit in Figure 1 uses a single NAND Schmitt-trigger IC . The circuit iscost-effective than dedicated, commercially available watchdog IC s. The circuit generates an active-high reset signal upon power-up and remains in a low state as long as the control input receives pulses. Whenever the pulsing at the control input stops, whether the circuit is in a high or a low state, th Design by VM Holla, Bangalore, India
Circuit Techniques for Clock Sources - Linear Technology AN12 __ Designed by Jim Williams - Oct 1st, 1985
Circuit times bathroom fan - 04/27/00 EDN Design Ideas: Forget to turn off the ceiling fan in your bathroom? install the simple timer in Figure 1 . it's located out-of-sight in the fan unit, and you turn it on via the wall switch. The circuit costs virtually nothing, using "junk" parts. When ac power appears, a simple rectifier develops approximately 7V across filter capacitor C. Design by Maxwell Strange, Goddard Space Flight Center, Fulton, MD
Clark Zapper - This is the circuit for Dr. Hulda Clark's Zapper, designed in 2003. The frequency is approximately 30kHz positive offset square wave. it has a red LED light that lights up when the unit is on. Perfect for regular zapping, extended zapping and other Hulda Clark related experiments__ 555-Timer
Clear Glass Sensor - industrial grade clear glass sensor modules are widely available but not within the reach of an average electronics hobbyist. The simple clear glass sensor circuit can be used for experiment/hobby purposes. The concept is very simple and is based on a home-made sensor unit comprising one high efficiency ultra bright red LED __ Designed by T.K. Hareendran
Clock Controller using AT89C205 vrs 1.1 - The Clock Controller V1.1was designed to be an exemplary of using 'C' language to control timer0interrupt, 7-segment LED and keypad scanning. it provides 1-bit sink currentdriving output, for driving a relay, opto-TRIAC, say. Many projects requiring7-segment display and keypad interfacing may get the idea from the Clockcircuit and software. __ Designed by Wichit Sirichote
Clock Fail Switches to Alternate Clock - 10/24/96 EDN Design Ideas: A common design need is to detect the presence or absence of a clock signal. in the absence of a clock, it may be necessary to switch to an alternate clock or to at least notify the system that a failure has occurred. The circuit in Figure 1 uses a silicon delay line to anticipate when the next clock cycle is due Design by Rick Downs, Dallas Semiconductor, Dallas, TX
Clock Generator - Use4093 oscillator. __ Designed by Tony van Roon VA3AVR
Clock multiplier circumvents PLL - 05/13/99 EDN Design Ideas: Using a standard PLL circuit, such as the CMOS
4046B with some passive components, is a wellknown way to design a clock multiplier. Design by Jose Carlos Cossio, Santander, Spain
Clock Pulse Generator - For many years the author has been approached by people who have managed to lay hands on an ‘antique’ electric clock and need an alternating polarity pulse driver. This is immediately followed. must register on this site __ Designed by Published in Elecktor July/Aug, 2010
Clock Recovery PLL Fits into Single PLD - 11/23/95 EDN Design Ideas: Serial-communication ICs can save you from using an extra wire thanks to an internal PLL clock-recovery circuit that reconstructs a clock signal phase-locked to the serial data stream. Design by Ricardo Monleone, AGIE Ltd, Losone, Switzerland
Clock Recovery Scheme Suits Low-SNR Systems - 06/05/00 EDN Design Ideas: A clock-recovery architecture can operate with NRZ digital signals, even at low SNRs. A clock-recovery subsystem is based on a PLL comprising a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO) Design by Luis Miguel Brugarolas, SIRE, Madrid, Spain
Clock Switching Banishes Glitches - 12/19/96 EDN Design Ideas: Many of today's digital systems require multiple clock domains as well as the ability to switch between them on the fly without producing glitches. Listing 1 consists of synthesizable VHDL code for such a circuit. in the circuit, two lines choose from among four input clocks to produce an output clock. The internal logic consists of a 2-to-4 line decoder, four identical clock-enabler logic blocks, and a 4-to-1 line multiplexer. You can easily customize the circuit for your application once you understand the basic concept. Design by Alex Sumarsono, Bay Networks Inc, San Jose, CA
Clock Timer - With this simple clock-controlled timer, you will never again miss your favourite TV or radio programme. The TV or radio will switch on automatically at the time preset by you and...__ Electronics Projects for You
Clock Tunable, Filter Based Sine Wave Generator - A feedback loop enclosed resonator can be made to oscillate. This circuit’s sine wave generator takes advantage of this and eliminates the need for an amplitude control loop. This circuit, a mildly modified form of the Regan resonant bandpass loop, is clock tunable and produces sine and cosine outputs. __ Linear Technology/Analog Devices App Note, Mar 26th 2010
Clock Tuned, Highly Selective Notch Filter - This circuit shows a quick, clean way to tune a notch filter’s center frequency by varying a single resistor, which could be switched. The LTC1062 switched capacitor filter and A1 form a clock tunable notch (see LTC1062 data sheet). O1, running from the 5V supply, furnishes the clock, which is level shifted by Q1 to drive the ±5V powered LTC1062. in this case, three common notch frequencies are listed; others are selectable by tuning O1 in accordance with the equivalency listed__ Linear Technology/Analog Devices App Note, Mar 26th 2010 |
