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Clock Circuits Page 2
Clocks: #-C D-G H-O P-S T-Z
Last Updated on: Friday, August 29, 2008 02:32 PM

Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

DC Power Wire also Carries Clock or Data: 03/13/98 EDN-Design Ideas / (added 6/06) -High-side current-sense amplifier, IC1, offers a simple method of combining low-speed clocks or other signals with dc power in cables between subsystems

DDR2: The Next Generation Main Memory: Pericom Semiconductor App Note # 078 (app note added 02/05)

Delay Line has Wide Duty Cycle Range: 06/27/02 EDN Design Ideas / (added 1/05) Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%. A limited range of available delays (2 to 100 nsec per tap) further limits their use. Longer delay is available with one-shot multivibrators of standard digital-logic families, ......

Delay Line Implements Clock Doubler: 12/19/96 EDN-Design Ideas / (added 3/03)

Design Guidelines for PC100 Registered SDRAM Modules: Pericom Semiconductor App Note # 013 (app note added 02/05)

Design Guidelines for Registered DDR Dimm Module using PI74ssTV16857 Registers and PI6cv857 PLL Drivers: Pericom Semiconductor Application Note # 037 (app note added 02/05)

Design Guides of PC133/100 Registered SDRAM Module: Pericom Semiconductor App Note # 020 (app note added 02/05)

Designing for Minimal Jitter When using Clock Buffers: Pericom Semiconductor Application Note # 024 (app note added 02/05)

Differences of Pericom Superclocks and Competitor Programmable Skew Clocks: Pericom Semiconductor Application Note # 061 (app note added 02/05)

Digital Clock with Timer and Solar Panel Regulator: This is a combination digital clock timer and solar panel charge controller used to maintain a deep cycle battery from a solar panel. The timer output is used to control a 12 volt load for a 32.... (added 2/07)

Digital LED Clock and Timer: (circuit / schematic design added 6/06)

Direct Digital Synthesizers in Clocking Applications Time Jitter in Direct Digital Synthesizer-Based Clocking Systems: AN-823 Analog Devices Application Notes (app note added 2/06)

Don't let Slow circuits Slow down the system : 08/17/98 EDN-Design Ideas / (added 2/06)

Dynamic Clock Provides for Zero Wait States: 03/27/97 EDN-Design Ideas / (added 3/06)

Emi Reduction Techniques: Pericom Semiconductor App Note # 011 (app note added 02/05)

Frequently Asked Questions on DDR Applications: Pericom Semiconductor Application Note # 027 (app note added 02/05)

Gated Clock has Duty-Cycle Control: 08/17/00 EDN-Design Ideas / (added 1/06) The circuit in Figure 1 produces clock pulses with variable duty cycle from a gated clock. The output of the circuit, pulse, is always 180° out of phase with the clock input. When the delay-logic elements, IC5 and IC7, have the same propagation delays, the duty cycle of the circuit's output is 50%. The circuit ....

General Routing Techniques with Emphasis on PI6c10x Clocks: Pericom Semiconductor App Note # 008 (app note added 02/05)

Generating Multiple Clock Outputs from the AD9540: AN-769 Analog Devices Application Notes (app note added 2/06)

Clocks: #-C D-G H-O P-S T-Z