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Clock Circuits:  A - B      C - D      E - P      Q - Z

 

Last Updated: October 24, 2017 02:54 PM

Circuits Designed by  Dave Johnson, P.E.

Camera Shutter Time Measurement  -  A while back I received an email from someone who needed a simple way to measure the speed of a photographic camera.  I thought about this and suggested the method below.  It relies on an oscilloscope and a cheap photodiode to measure the speed . . . Hobby Circuit designed by Dave Johnson P.E.-August 14, 2011

Chicken Coop Door Opener with Timer  -  I received an email from a guy in Australia who was trying to build a chicken coop system.  He was planning on using a conventional garage door mechanism to open and close the 6 doors to the coop.  The commercial door opener opened and closed the doors with a single pushbutton.  He wanted to install a standard 220vac powered timer so he could open the doors in the morning and close them at night . . . Circuit by Dave Johnson P.E.-March 24, 2013

Closet Light with Automatic 3-Minute Timeout  -  The circuit below is powered by three 1.5v alkaline AA cells. With a finger tap to the pushbutton trigger switch, a cluster of 6 wide angle white LEDs is turned on. The lights remain on for about 3 minutes, then will turn off. The circuit’s standby current is only a few microamps. A set of fresh batteries should last at least 200 light applications. The circuit uses a Schmitt trigger inverter and two transistors. When the pushbutton switch S1 is pressed, the 10uF capacitor C1 is discharged. . .  David A. Johnson P.E.-November 14, 2010

Computer, Long Period, Watch Dog Timer  -  This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer. Should the computer fail to send a pulse, the output changes state. The time can easily be set from seconds to hours. . . Hobby Circuit designed Dave Johnson P.E.-December 26, 1998

Count Cars with Laser  -  This is an illustration how a laser could be used to count traffic and measure the speed of each car passing through the sensor area . . . Hobby Circuit designed by David A. Johnson P.E.-July 09, 2006

Darkroom Camera Shutter Timer  -  This circuit was designed to control a film exposure shutter for a darkroom.  It has 8 time steps ranging from 0.35 seconds to 4 seconds.  It is activated by a foot switch and draws power from an external 12-volt DC supply__ Designed by David Johnson P.E.-June 11, 2000

Digital Counter using Pedometer  -  There are many occasions when you may want to count something electronically.  Perhaps it is car traffic on a street or items moving down an assembly line.  It might be the number of times a machine is activated or maybe you want to count the number of . . . Hobby Circuit designed by David Johnson P.E.-August 17, 2008

Divide a TTL Clock Signal by 1.6  -  Two inexpensive ICs  divide a TTL clock signal by 1.5.  By following the circuit with another flip/flop, you could also generate a divide by three function . . . Hobby Circuit designed by David Johnson P.E.-July 06, 2000

Divide By 1.5 Counter  -  Two inexpensive ICs  divide a TTL clock signal by 1.5.  By following the circuit with another flip/flop, you could also generate a divide by three function . . . Circuit by David Johnson P.E.-July 06, 2000


Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

Camera Shutter Time Measurement  -  A while back I received an email from someone who needed a simple way to measure the speed of a photographic camera.  I thought about this and suggested the method below.  It relies on an oscilloscope and a cheap photodiode to measure the speed . . . Hobby Circuit designed by Dave Johnson P.E.-August 14,2011

Camera Shutter Timer  -  This was a quick hack to measure camera shutter speeds, motivated by my finding out that my first SLR (an Olympus OM-10 purchased secondhand a few months earlier) had a shutter problem. After I had the camera repaired, I used this to check that the shutter speeds were OK, and later used it to test various mechanical shutters on other cameras. __ Designed by Markus Wandel

Chicken Coop Door Opener with Timer  -  I received an email from a guy in Australia who was trying to build a chicken coop system.  He was planning on using a conventional garage door mechanism to open and close the 6 doors to the coop.  The commercial door opener opened and closed the doors with a single pushbutton.  He wanted to install a standard 220vac powered timer so he could open the doors in the morning and close them at night . . . Circuit by Dave Johnson P.E.-March 24,2013

Circuit allows high-speed clock multiplication  -  05/02/02 EDN Design Ideas:     in theory, synchronous clock multiplication is an easy task.   A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator] and the second one placed directly at the input of the phase detector—may do the job.   The flexibility of such a configuration allows for clock multiplication by any rational number __ Circuit Design by Lukasz Sliwczynski and Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow, Poland

Circuit avoids metastability  -  08/30/01  EDN Design Ideas:  Consider a computer system that has a host processor connected to a remote-i/O subsystem (Figure 1).  The host clock treats the i/O system, which is located far from the main hardware, as a slave.  Because of the transmitters, receive __ Circuit Design by Jonathan Eckrich, Adaptivation, Sioux Falls, SD

Circuit conditions variable-duty-cycle clock  -  02/17/97 EDN Design Ideas:     Simple enhancement of an earlier Design idea ("Delay line implements clock doubler", EDN, July 18, 1996, pg 102) implements a variable-duty-cycle clock-signal conditioner.   The circuit accepts an input clock of any duty cycle and generates any desired duty cycle at the output.   You need to add only one flip-flop to the earlier design to generate an arbitrary-duty-cycle output.   You can use the circuit to correct a non-50% input to a 50% output or to create a non-50% output from any arbitrary input duty cycle __ Circuit Design by David Albean, Thomson Consumer Electronics, Indianapolis, IN

Circuit gates pulse train without truncating  -  EDN Design Ideas:  Jan 12, 2015   To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task.  In most cases, a simple AND gate will cause problems, see Figure 1.   Clock pulses pass through the AND gate as long as the asynchronous strobe E is high.  If loss or distortion of even one pulse is critical, then the simple AND gate is unsuitable, as the first and the last pulse in the burst will often be distorted (shorter than usual pulse) due to the lack of synchronization between clock and E. __ Circuit Design by Viktor Safronov

Clock Controller Using AT89C2051  -  The Clock Controller V1.1was designed to be an exemplary of using 'C' language to control timer0interrupt, 7-segment LED and keypad scanning.  It provides 1-bit sink currentdriving output, for driving a relay, opto-TRIAC, say. Many projects requiring7-segment display and keypad interfacing may get the idea from the Clockcircuit and software. __ Designed by Wichit Sirichote

Clock Controller Using AT89C2051 1  -  The Clock Controller V1.1was designed to be an exemplary of using 'C' language to control timer0interrupt, 7-segment LED and keypad scanning.  It provides 1-bit sink currentdriving output, for driving a relay, opto-TRIAC, say. Many projects requiring7-segment display and keypad interfacing may get the idea from the Clockcircuit and software. __ Designed by Wichit Sirichote

Clock Fail Circuit Switches to Alternate Clock  -  10/24/96 EDN Design Ideas:     A common design need is to detect the presence or absence of a clock signal.   in the absence of a clock, it may be necessary to switch to an alternate clock or to at least notify the system that a failure has occurred.   The circuit in Figure 1 uses a silicon delay line to anticipate when the next clock cycle is due __ Circuit Design by Rick Downs, Dallas Semiconductor, Dallas, TX

Clock Generator  -  Use4093 oscillator. __ Designed by Tony van Roon (VA3AVR)

Clock multiplier circumvents PLL  -  05/13/99 EDN Design Ideas:  Using a standard PLL circuit, such as the CMOS 4046B with some passive components, is a wellknown way to design a clock multiplier.   __ Circuit Design by Jose Carlos Cossio, Santander, Spain

Clock Pulse Generator  -  For many years the author has been approached by people who have managed to lay hands on an ‘antique’ electric clock and need an alternating polarity pulse driver. This is immediately followed. must register on this site__ Designed by Published in Elecktor July/Augu, 2010

Clock Recovery PLL Fits into Single PLD  -  11/23/95 EDN Design Ideas:     Synchronous serial protocols, HDLC, for example, require that you synchronize the transmitter and the receiver. Sometimes, this synchronization requires an extra wire to carry the serial clock. However, many serial-communication ICs  can save this wire thanks to an internal PLL clock-recovery circuit that reconstructs a clock signal phase-locked to the serial data stream.  __ Circuit Design by Ricardo Monleone, AGIE Ltd, Losone, Switzerland

Clock Recovery Scheme Suits Low Snr Systems  -  06/05/00 EDN Design Ideas:     A clock-recovery architecture can operate with NRZ digital signals, even at low SNRs. A clock-recovery subsystem is based on a PLL comprising a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO)  __ Circuit Design by Luis Miguel Brugarolas, SIRE, Madrid, Spain

Clock Switching Circuit Banishes Glitches  -  12/19/96 EDN Design Ideas:     Many of today's digital systems require multiple clock domains as well as the ability to switch between them on the fly without producing glitches.   Listing 1 consists of synthesizable VHDL code for such a circuit.   in the circuit, two lines choose from among four input clocks to produce an output clock.   The internal logic consists of a 2-to-4 line decoder, four identical clock-enabler logic blocks, and a 4-to-1 line multiplexer.   You can easily customize the circuit for your application once you understand the basic concept.   __ Circuit Design by Alex Sumarsono, Bay Networks Inc, San Jose, CA

Clock Tuned, Highly Selective Notch Filter  -  This circuit shows a quick, clean way to tune a notch filter’s center frequency by varying a single resistor, which could be switched. The LTC1062 switched capacitor filter and A1 form a clock tunable notch (see LTC1062 data sheet). O1, running from the 5V supply, furnishes the clock, which is level shifted by Q1 to drive the ±5V powered LTC1062.  In this case, three common notch frequencies are listed; others are selectable by tuning O1 in accordance with the equivalency listed__ Linear Technology/Analog Devices App Note, Mar 26th 2010

Clock with Timer & Solar Panel Regulator  -  This is a combination clock timer and solar panel charge controller used to maintain a deep cycle battery from a solar panel. The timer output is used to control a 12 volt load for a 32__ Designed by Bill Bowden

Clock-recovery scheme suits low-SNR systems  -  06/05/00 EDN Design Ideas:     A clock-recovery architecture can operate with NRZ digital signals, even at low SNRs.   A clock-recovery subsystem is based on a PLL comprising a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO]PDF Contains many designs, scroll to find this one__  by Luis Miguel Brugarolas, SIRE, Madrid, Spain

Closet Light with Automatic 3-Minute Timeout  -  The circuit below is powered by three 1.5v alkaline AA cells. With a finger tap to the pushbutton trigger switch, a cluster of 6 wide angle white LEDs is turned on. The lights remain on for about 3 minutes, then will turn off. The circuit’s standby current is only a few microamps. A set of fresh batteries should last at least 200 light applications. The circuit uses a Schmitt trigger inverter and two transistors. When the pushbutton switch S1 is pressed, the 10uF capacitor C1 is discharged. . .  David A. Johnson P.E.-November 14,2010

Compute A Histogram In An FPGA With One Clock  -  02/03/11  EDN Design Ideas:     Use a histogram to analyze large amounts of data. Histograms are often useful tools for analyzing digital data. To get reliable results from a histogram, though, you must collect large amounts of data, often with 100, 000 to 1 million points.  If you need to collect an ADC’s digital outputs for analysis, you can use an FPGA (Figure 1).  __ Circuit Design by Mohit Kumar, Texas Instruments, Bangalore, India

Computer, Long Period, Watch Dog Timer  -  This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer. Should the computer fail to send a pulse, the output changes state. The time can easily be set from seconds to hours. . . Hobby Circuit designed Dave Johnson P.E.-December 26,1998

Count Cars with Laser  -  This is an illustration how a laser could be used to count traffic and measure the speed of each car passing through the sensor area . . . Hobby Circuit designed by David A. Johnson P.E.-July 09,2006

Coupling a Single-Ended Clock Source to the Differential Clock Input of Third-Generation TxDAC® & TxDAC+® Products  -  AN-642 Analog Devices App Note__

Crosstalk on the Clock Part 2  -  App Note/ 1841 / Nov-04__ Maxim Integrated

Crystal Considerations with Dallas Real-Time Clocks RTCs  -  Application Note #58__ Maxim Integrated

Darkroom Camera Shutter Timer  -  This circuit was designed to control a film exposure shutter for a darkroom.  It has 8 time steps ranging from 0.35 seconds to 4 seconds.  It is activated by a foot switch and draws power from an external 12-volt DC supply__ Designed by David Johnson P.E.-June 11,2000

DC Power Wire also Carries Clock or Data  -  03/13/98 EDN Design Ideas:  NOTE:  File contains many circuits, please scroll to find this one.  High-side current-sense amplifier, IC 1, offers a simple method of combining low-speed clocks or other signals with dc power in cables between subsystems __ Circuit Design by Mike Hardwick, Decade Engineering, Turner, OR

Dekatron-device used for dividing by 10 during the valve era  -  The circuit diagram is almost the same as Mike's.  I added an ON/OFF switch and an additional toggle switch to stop the spin.  The resistors are standard types (according to Mike I should've used higher power ones to ensure adequate voltage rating) ; the capacitors need to have sufficient voltage rating.  I didn't have anything rated 400V so I used two 330nF capacitors in series in two places.   __ Designed by Hans Summers

Delay line has wide duty-cycle range  -  06/27/02 EDN Design Ideas:  Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%.  A limited range of available delays (2 to 100 nsec per tap] further limits their use.  Longer delay is available with one-shot multivibrators of standard digital-logic families, but those devices do not retain duty-c __ Circuit Design by John Guy, Maxim Integrated Products, Sunnyvale, CA

Delay Line implements Clock Doubler  -  Timing delays are undesirable in most digital circuits.  However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example.  The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler.  Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock.  Using a more precise delay line, the circuit can output a triple clock (Figure 1b).   __ Circuit Design by Y Li, SAE magnetics  HK Ltd, Guang Dong Province, China - 7/18/96

Digital clock based on 74 series logic  -  With pleasure the lot of friends of digital clocks that use discernible components, will see this circuit.  It's a clock, with 12hour clue, little simpler in the manufacture from the SamClock.  It�s a designing that became from the friend George Kordogiannis in 1990, which was modified and corrected in enough points by my, until it reach in the current form. Most completed that uses is TTL, apart from the IC 9 until IC 13, that is CMOS, that they have the faculty to drive display Common Cathode__ Designed by Sam Gordon

Digital clock that receives & displays the time from the Rugby MSF radio transmission (PIC16F877)  -  A digital clock which receives and displays the time from the MSF radio transmission, broadcast from Anthorn, Cumbria (54°55'N, 3°17'W). __ Designed by © Chris Johnson

Digital Clock With Alarm Using DS1307  -  DS1307 is a hardware realtime clock, which works on i2C protocol. Better graphics using the same old fashioned alphanumeric LCD (type HD44780).  Icons which shows the status for Alarm ON/OFF state, which gives a nice and cute look to the clock. __ Designed by Ajay Bhargav, ajay_bhargav @ hotmail.com

Digital Clock with Timer & Solar Panel Regulator  -  This is a combination digital clock timer and solar panel charge controller used to maintain a deep cycle battery from a solar panel. The timer output is used to control a 12 volt load for a 32. __ Designed by Bill Bowden

Digital Counter using Pedometer  -  There are many occasions when you may want to count something electronically.  Perhaps it is car traffic on a street or items moving down an assembly line.  It might be the number of times a machine is activated or maybe you want to count the number of . . . Hobby Circuit designed by David Johnson P.E.-August 17,2008

Digital Stopwatch  -  times up to an hour in tenths of a second -__ Conact P. Townshend - EduTek Ltd

Digital Timer With 7-Segment Display & Pushbuttons  -  The original version of xTimer used MAX7219 for driving 7-segment. This new design uses a cheap CMOS shift register, 4094 for LED interface. Each 4094 drives a 0.5" 7-segment without the need of limiting resistor. The left-hand LED is timer function with buzzer alarm output. The right-hand is for clock display. __ Designed by Wichit Sirichote

Divide a TTL Clock Signal by 1.6  -  Two inexpensive ICs  divide a TTL clock signal by 1.5.  By following the circuit with another flip/flop, you could also generate a divide by three function . . . Hobby Circuit designed by David Johnson P.E.-July 06,2000

Divide By 1.5 Counter  -  Two inexpensive ICs  divide a TTL clock signal by 1.5.  By following the circuit with another flip/flop, you could also generate a divide by three function . . . Circuit by David Johnson P.E.-July 06,2000

Don't let Slows Slowdown the system  -  08/17/98 EDN Design Ideas:  NOTE:     FILE has several circuits, scroll to this one.  A combinatorial function with a propagation delay greater than the system clock period does not necessarily prevent a design from operating at frequency.  By taking advantage of arrival times or carefully using wait states, a design can give the combinatorial circuit sufficient time to settle before __ Circuit Design by Kevin Skahill, Cypress Semiconductor, San Jose, CA

Dynamic clock provides for zero wait states  -  03/27/97 EDN Design Ideas:     The clock controller in Figure 1, which you can implement in a PLD, dynamically manipulates the timing of synchronous FiFO clock and control signals to provide for zero-wait-state accesses.   These zero wait states would be otherwise impossible with a fixed clock design.    This concept __ Circuit Design by Mike Nelson, Polaris Communications Inc, Portland, OR


Clock Circuits:   A - B      C - D      E - P      Q - Z

 


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