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Clock Circuits  Page 3
Clocks:   #-A      B-C      D-G       H-O      P-S      T-Z

Last Updated on: Wednesday, July 16, 2014 06:34 AM

 

Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:
DC Power Wire also Carries Clock or Data -  03/13/98 EDN-Design Ideas  High-side current-sense amplifier, IC1, offers a simple method of combining low-speed clocks or other signals with dc power in cables between subsystems.... [Design Idea by Mike Hardwick, Decade Engineering, Turner, OR]
DDR2: The Next Generation Main Memory -  Pericom Semiconductor App Note # 07)8 (app note added 02/05)
Delay line has wide duty-cycle range -  27-Jun-02 Issue of EDN  Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%. A limited range of available delays (2 to 100 nsec per tap] further limits their use. Longer delay is available with one-shot multivibrators of standard digital-logic families, but those devices do not retain duty-c.... [Design Idea by By John Guy, Maxim Integrated Products, Sunnyvale, CA]
Delay Line implements Clock Doubler -  07/18/96 EDN-Design Ideas  [Design Idea added 3/03] EDN is migrating links. This link is not verified.  Google the "title" EDN for new link.

Designing for Minimal Jitter When using Clock Buffers -  Pericom Semiconductor Application Note # 024 (app note added 02/05)
Differences of Pericom Superclocks & Competitor Programmable Skew Clocks -  Pericom Semiconductor Application Note # 061 (app note added 02/05)
Digital Clock with Timer & Solar Panel Regulator -  This is a combination digital clock timer and solar panel charge controller used to maintain a deep cycle battery from a solar panel. The timer output is used to control a 12 volt load for a 32. [Bill Bowden]
Direct Digital Synthesizers in Clocking Applications Time Jitter in Direct Digital Synthesizer-Based Clocking Systems -  AN-823 Analog Devices Application Notes  (app note added 2/06)  
Don't let Slow circuits Slow down the system -  08/17/98 EDN-Design Ideas  A combinatorial function with a propagation delay greater than the system clock period does not necessarily prevent a design from operating at frequency. By taking advantage of arrival times or carefully using wait states, a design can give the combinatorial circuit sufficient time to settle before....File has several circuits, scroll to this one.... [Design Idea by Kevin Skahill, Cypress Semiconductor, San Jose, CA]
Dynamic Clock Provides for Zero Wait States -  03/27/97 EDN-Design Ideas  The clock controller in Figure 1, which you can implement in a PLD, dynamically manipulates the timing of synchronous FIFO clock and control signals to provide for zero-wait-state accesses. These zero wait states would be otherwise impossible with a fixed clock design.  This concept.... [Design Idea by Mike Nelson, Polaris Communications Inc, Portland, OR]
Emi Reduction Techniques -  Pericom Semiconductor App Note # 011 (app note added 02/05)
Fail-Safe Monitoring & Clock Frequency Switching using the PIC16f684 -  Microchip Application Note Published 16-Dec-03  (app note added 2/06)
Frequently Asked Questions on DDR Applications -  Pericom Semiconductor Application Note # 027 (app note added 02/05)
Garden Timer with Remote control -  Few years ago we control the lights in the garden with a automatic-timer-switch, very nice but when the evening gets longer or shorter we had to adapt the timer each week. In that time I came in contact with programming microprocessors so my first project was born. The first garden timer was a simple 1 output. The timing was controlled by the PIC and every month I had to change the minutes. So back to the table and design the second garden timer able to control 3 relays, left, mid and right side of the garden. It provided also 4 modes: always off always on from dusk to dawn from dusk to timer and the timing was dedicated to a RTC DS1307. .(design added 11/08)
Gated Clock has Duty Cycle Control -  08/17/00 EDN-Design Ideas  The circuit in Figure 1 produces clock pulses with variable duty cycle from a gated clock. The output of the circuit, pulse, is always 180 out of phase with the clock input. When the delay-logic elements, IC5 and IC7, have the same propagation delays, the duty cycle of the circuit's output is 50%. The circuit....[Design Idea added 1/06] EDN is migrating links. This link is not verified.  Search the "title" EDN for new link.
General Routing Techniques with Emphasis on PI6c10x Clocks -  Pericom Semiconductor App Note # 008 (app note added 02/05)
Generating Multiple Clock Outputs from the AD9540 -  AN-769 Analog Devices Application Notes  (app note added 2/06)  

Clocks:   #-A      B-C      D-G       H-O      P-S      T-Z
 


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