16 Bit Risc Processor:  with five pipeline stages.  instruction set implements ALU, immediate, load, store, and branch instructions. (added 4/02)

2 Gates Expand ASIC's Memory-Decoding Range:  03/29/01 EDN-Design Ideas / (added 2/06)  Many electronic circuits implement chip-select lines on an ASIC. From  beginning of  design cycle,  chip selects, CS0 to CS4, have defined bases on  memory map (Figure 1). Adding functions to  product requires increasing  DRAM space. Now, you must redesign  ASIC so  chip select, CS1, can accommodate  new memory space of 04000000 to 0BFFFFFF.
 circuit in Figure 2 uses two external exclusive-OR gates to expand memory-address-decoding space for  CS1 signal from  initial range of 04000000 to 07)FFFFFF to 04000000 to 0BFFFFFF. When address line A27 is low, exclusive-OR gates IC1A and IC1B allow A27 and A26 signals to pass through unchanged. In this case...

Add a Schmitt Trigger Function to Cplds FPGAs and Applications:  10/13/05   EDN -Design Ideas  / (added 11/05)   For slow-slewing signals, hysteresis solves trigger problem.

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications:  10/13/2005  EDN Design Ideas  / (added 02/07)    For slow-slewing signals, hysteresis solves trigger problem.

AN-1126: BGA  (Ball Grid Array):  National Semiconductor Application Note   (app note added 2/06)

AN-1327: Simplified Programming of Altera FPGA's using a Scansta111/112 Scan Chain Mux:  National Semiconductor Application Note   (app note added 2/06)

AN-1376: External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs:  National Semiconductor Application Note   (app note added 6/06)

Audio Project:  for  XSV Board (Univ. of Queensland) (added 4/02)

Audio Volume Indicator:  uses an XS40 Board and XStend Board to display  volume of an audio input on a barograph LED. (added 4/02)

BGA  (Ball Grid Array):  National Semiconductor Application Note   (app note added 2/06)