Calculator Program Evaluates Elliptic Filters:  03/31/05 EDN Design Ideas  / (added 11/05)  Find  poles and zeroes of elliptic-filter designs using Darlington’s algorithm implemented on a calculator.

Calculator Program Finds Closest Standard Resistor Values:  02/03/05 EDN Design Ideas  / (added 5/05)  Although it may not appear obvious to newcomers to  electronics-design profession, components' values follow one of several progressions that divide a decadewide span into equally spaced increments on a logarithmic scale. For example, when you plot  values of 1, 2.2, and 4.7 on a logarithmic scale, y divide  range 1 to 10 into three roughly equal increments (1.

Calculator:  uses  8051 microcontroller and FPGA on  XS40 Board to build a simple calculator. (added 4/02)

Circuit Allows High Speed Clock Multiplication:  05/02/02 EDN Design Ideas  / (added 11/05)  In theory, synchronous clock multiplication is an easy task. A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator) and the second one placed directly at the input of the phase detector—may do the job. The flexibility of such a configuration allows for clock multiplication by any rational number.

Circuit Protects FPGAs from killer SPICEs :  04/23/98 EDN-Design Ideas  /  (added 06/03) [Note: File contains many circuits, scroll to find this one] A project using Xilinx FPGAs brought an interesting problem to light. When you turn on the board, one FPGA in three succumbs to this problem. A lot of frustration and testing uncovered a negative-going spike (Figure 1) in the 5V line from the dc/dc converter. The system uses a dc/dc converter to convert 48V to 5V and other voltages. The spike occurs before the converter delivers its intended 5V. Spikes greater than 5V would kill the FPGA with the shortest path to the converter. The circuit in Figure 2 solves the problem.....

Circuit Provides Power Sequencing:  10/14/04 EDN Design Ideas  / (added 10/05)  AS ICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing. Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last. This scenario may also require that one supply rail not exceed another by more than a diode drop; otherwise, excessive c...

Circuit sequences supplies for FPGAs:  01/23/03  EDN-Design Ideas / (added 6/06) System designers must consider the timing and voltage differences between core and I/O power supplies (in other words, power-supply sequencing) during power-up and power-down. The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly. The trigger for latch-up may occur if power supplies apply different potentials to the core and .....

CPLD automatically powers itself off:  4/13/2006    EDN Design Ideas  / (added 02/07)    Add a few discrete components to a CPLD to implement a battery-powered system's power-down circuit.

CPLD Interface Files:  for the XSV Board projects (Univ. of Queensland)  (added 4/02)