|
Gate Array Circuits
Page 2
Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z
Last Updated on:
Monday, October 03, 2011 06:07 PM |
|
|
Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
|
|
Calculator - uses 8051 microcontroller and FPGA on XS40 Board to
build a simple calculator. (added 4/02) |
|
Calculator program evaluates elliptic filters - 31-Mar-05 Issue of EDN
Find the poles and zeroes of elliptic-filter designs using Darlington’s algorithm
implemented on a calculator..... [Design Idea by Fernando Salazar-Martínez, Alan
Altamirano-Cruz, and David Báez-López, Department of Engineering Electronics,
University of the Americas, Puebla, Mexico; Edited by Brad Thompson] |
|
Calculator program finds closest standard resistor values - 3-Feb-05 Issue
of EDN Although it may not appear obvious to newcomers to the electronics-design
profession, components' values follow one of several progressions that divide a
decadewide span into equally spaced increments on a logarithmic scale. For example,
when you plot the values of 1, 2.2, and 4.7 on a logarithmic scale, they divide the
range 1 to 10 into three roughly equal increments (1..... [Design Idea by Francesc
Casanellas, Aiguafreda, Spain] |
|
|
|
|
|
Camera Interface - project shows how a CMOS ‘Camera On a
Chip’ image sensor can be interfaced to an XSA-100 Board through an
I2C bus. The pixel data is buffered in the XSA-100 SDRAM and is then
uploaded through the parallel port to be displayed on a PC. (added
4/02) |
|
Circuit allows high-speed clock multiplication - 2-May-02
Issue of EDN In theory, synchronous clock multiplication is an
easy task. A simple PLL with two digital dividers—one inserted just
after the VCO (voltage-controlled oscillator] and the second one
placed directly at the input of the phase detector—may do the job. The
flexibility of such a configuration allows for clock multiplication by
any rational number..... [Design Idea by Lukasz Sliwczynski and
Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow,
Poland] |
|
Circuit Protects FPGAs from killer SPICEs - 04/23/98 EDN-Design
Ideas.....A project using Xilinx FPGAs brought an interesting problem
to light. When you turn on the board, one FPGA in three succumbs to
this problem. A lot of frustration and testing uncovered a
negative-going spike (Figure 1]in the 5V line from the dc/dc
converter. The system uses a dc/dc converter.....File contains many
circuits, scroll to find this one..... [Design Idea by Nelson Nguyen,
Anritsu Corp, Morgan Hill, CA] |
|
|
|
Circuit Provides Power Sequencing - 10/14/04 EDN-Design Ideas.....AS
ICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on
their start-up sequencing. Often, I/O voltages, which usually have the highest
voltage, must come up first, followed by all other voltage rails in a high-to-low
order, with the core voltage last. This scenario may also require that one
supply rail not exceed another by more than a diode drop; otherwise, excessive
c..... EDN is migrating links. This link is not verified. Search the "title"
EDN for new link. |
|
Circuit sequences supplies for FPGAs - 23-Jan-03 Issue of EDN
System designers must consider the timing and voltage differences between core and
I/O power supplies (in other words, power-supply sequencing] during power-up and
power-down. The possibility of a latch-up failure or excessive current draw exists
when power-supply sequencing does not occur properly. The trigger for latch-up may
occur if power supplies apply different potentials to the core and..... [Design
Idea by David Daniels, Texas Instruments, Dallas, TX] |
|
CMOS Gate Implements Reverse Phase Control - 05/21/98 EDN-Design
Ideas.....The circuit in Figure 1 implements a "reverse" phase control, using only
a single CMOS 4001 quad NOR gate. The circuit is known as a reverse phase control
because, unlike with common triac or SCR controls, conduction begins at the zero
crossing of the ac sine wave. Timing of the turn-off point.....File has seeveral
circuits, scroll down..... [Design Idea by JC Johnson, Lithonia Lighting, Decatur,
GA] |
|
Configuring HEART, statically or dynamically - (added 5/08) |
|
Connecting the PowerPC Processor to Hardware - (added 5/08) |
|
Converting your FPGA design from Hardware Interface Layer V1.x to V2.x -
(added 5/08) |
|
CPLD automatically powers itself off - 13-Apr-06 Issue of EDN Add
a few discrete components to a CPLD to implement a battery-powered system's
power-down circuit..... [Design Idea by Rafael Camarota, Altera Corp, San Jose,
CA; Edited by Brad Thompson and Fran Granville] |
|
CPLD autonomously powers battery powered system - 12-Apr-07 Issue of EDN
CPLD controls power-on and off of intermittent-battery-powered system..... [Design
Idea by Rafael Camarota, Altera Corp, San Jose, CA; Edited by Charles H Small and
Brad Thompson] |
|
CPLD Interface Files - for the XSV Board projects (Univ. of Queensland)
(added 4/02) |
|
CPLD’s internal oscillator performs autocalibration - 13-Sep-07 Issue of
EDN An autocalibration sequence synchronizes a CPLD's internal oscillator
with an external crystal oscillator, enabling ±0.3% accuracy..... [Design Idea by
Rafael Camarota, Altera Corp, San Jose, CA] |
|
|
|
|
|
|
| Gate Arrays:
#'s - B, C,
D - I, J - P,
Q - U,
V - Z |
|
|
