Sequence Supplies for FPGAS - 01/23/03 EDN-Design Ideas System designers must consider the timing and voltage differences between core and I/O power supplies(in other words, power-supply sequencing] during power-up and power-down. The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly. The trigger for latch-up may occur if power supplies apply different potentials to the core and__ Circuit Design by David Daniels, Texas Instruments, Dallas, TX
Simple Circuit FIFO provides data-width conversion - 09/26/02 EDN-Design Ideas Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in __ Circuit Design by David Lou, Ghent University, Ghent, Belgium
Simple Circuit provides power sequencing - 14-Oct-04 EDN-Design Ideas ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing. Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last. This scenario may also require that one supply rail not exceed another bythan a diode drop; otherwise, excessive c__ Circuit Design by John Betten, Texas Instruments, Dallas, TX
Single-MOSFETs gate & Modulate - EDN-Design Ideas 07/27/2015 The humble discrete MOSFET shows its versatility in This design idea __ Circuit Design by Umar Shami
Swapping bits improves performance of FPGA PWM counter - 09/13/07 EDN-Design Ideas A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC__ Circuit Design by Stefaan Vanheesbeke, Ledegem, Belgium
Tool generates HDLs directly from Simulink - 09/19/06 EDN-Design Ideas The folks trying to model multiple DSP functions to implement in FPGAs or ASICs using MathWorks tools will be happy to learn that the company's latest release, Simulink HDL Coder, automatically generates cycle-accurate, bit-accurate Verilog or VHDL directly from Simulink__ Circuit Design by Michael Santarini, Senior Editor -- EDN
Two Gates Expand ASICs Memory Decoding Range - 03/29/01 EDN-Design Ideas Many electronic circuits implement chip-select lines on an ASIC. From beginning of design cycle, chip selects, CS0 to CS4, have defined bases on memory map (Figure 1). Adding functions__ Circuit Design by Vinh Hoang, Ericsson Inc, Brea, CA
Two wires control SPI high-speed ADC - 11/10/05 EDN-Design Ideas Inverters substitute for an SPI ADC's chip-select line__ Circuit Design by Dan Meeks, Texas Instruments Inc, Austin, TX
USB Macro - that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions. This macro was developed and is supported by Trenz Electronics for use with an XSV Board __
Virtex 5 Adds PCI Express & 10 Gbit Ethernet cores - 10/18/06 EDN-Design Ideas Xilinx has released the second platform derivative of its Virtex-5 FGPA family targeting markets requiring serial connectivity Design by Michael Santarini, Senior Editor -- EDN
Walking Bit - shifts a1 through a register mapped to the 7-segment LED. This design shows the interactions between the XC4000 FPGA and the 8031 microcontroller on the XS40 Board __ |