Digital Camera Interface:  project shows how a CMOS ‘Camera On a Chip’ image sensor can be interfaced to an XSA-100 Board through an I2C bus. The pixel data is buffered in the XSA-100 SDRAM and is then uploaded through the parallel port to be displayed on a PC. (Electronic Schematic / circuit added 4/02)

Dual Output Supply Powers FPGAs from 3.3V and 5V Inputs:  DN311 -  Design Notes (Linear Technology) (app note added 1/06)

External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs:  National Semiconductor - Application Note   (app note added 6/06)

Fast Integer Multipliers Fit in FPGAs:  05/12/94 EDN Design Ideas /  (added 2/06)

FIFO Provides Data Width Conversion:  09/26/02 EDN Design Ideas  / (added 1-/05)  Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1).

FPGA Circuit Emulates 74x74 Flip Flop:  10/12/95 EDN-Design Ideas / (added 11/05) 

FPGA Configuration Scheme is Flexible:  02/05/2004  EDN-Design Ideas  In low-noise analog circuits, a high-gain amplifier serves at the input to increase the SNR. The input signal level determines the input-stage gain; low-level signals require the highest gain. It is also standard practice in low-noise analog-signal processing to make the circuit's bandwidth as narrow as possible to pass only the useful input-signal spectrum. (added 10/05)

FPGA Configures Simple Bcd Adder:  02/15/96 EDN-Design Ideas / (added 11/05)

FPGA Implements X50 Division 3 Recommendation:  04/13/2000  EDN-Design Ideas  The scheme in Figure 1a uses five delay cells and an XOR gate to configure the data stream for the X.50 Division 3 recommendation of ITU-T. The X.50 recommendation defines the fundamental parameters of a multiplexing scheme for interworking data networks using different envelope structures. Division 3 applies to the interworking between two networks, both of which use the 8-bit envelope structure. (added 10/05)

FPGA Makes Simple FIFO:  10/26/00  EDN-Design Ideas  / (added 10/05) 

FPGA Transfers Data on Every Clock Cycle:  03/03/94 EDN Design Ideas / (added 2/06)

FPGA's Tri State Buffers Build 32x32 Crossbar:  12/08/94 EDN Design Ideas /  (added 2/06) 

Introduction to XS Volt Board Designs:  done by the University of Queensland (Electronic Schematic / circuit added 4/02)