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Gate Array Circuits
Page 3
Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z
Last Updated on:
Monday, October 03, 2011 06:07 PM |
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Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
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Digital Down Conversion theory - (added 5/08) |
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Dual Output Supply Powers FPGAs from 3.3V & 5V Inputs - DN311 Design
Notes (Linear Technology) (app note added 1/06) |
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External Memory Types for 'C6000 Systems - (added 5/08) |
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External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs -
National Semiconductor Application Note.....[App Note] |
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Fast Integer Multipliers Fit in FPGAs - 05/12/94 EDN-Design Ideas.....You
can fit a fast and compact digital multiplier into a field-programmable gate array (FPGA].
The technique involves using small look-up tables to find partial products and then
adding the partial products. The key factor for making the design compact, fast, and
easy to implement is to make the look-up tables for the partial products as small as
possible. This multiplier can quickly multiply a number by a constant; changing
the constant momentarily takes the multiplier off-line..... [Design Idea by Kenneth
David Chapman, Xilinx Ltd, Byfleet, Surrey, UK] |
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FIFO Provides Data Width Conversion - 09/26/02 EDN-Design Ideas.....Many
designs require FIFO elastic buffers to form a bridge between subsystems with
different clock rates and access requirements. However, in some applications, you need
FIFO buffers for data conversion. One example is the case in which you need to connect
an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1].....
EDN is migrating links. This link is not verified. Search the "title" + "EDN" for
new link. |
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Filters with HERON FPGA - (added 5/08) |
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FPGA Circuit Emulates 74x74 Flip-flop - 10/12/95 EDN-Design Ideas..... EDN
is migrating links. This link is not verified. Search the "title" + "EDN" for new
link. |
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FPGA Configures Simple BCD Adder - 02/15/96 EDN-Design Ideas EDN is
migrating links. This link is not verified. Search the "title" + "EDN" for new link.
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FPGA Implements X50 Division 3 Recommendation - 04/13/00 EDN-Design
Ideas.....The scheme in Figure 1a uses five delay cells and an XOR gate to configure
the data stream for the X.50 Division 3 recommendation of ITU-T. The X.50
recommendation defines the fundamental parameters of a multiplexing scheme for
interworking data networks using different envelope structures. Division 3 applies to
the interworking between two networks, both of which use the 8-bit envelope
structure..... EDN is migrating links. This link is not verified. Search the
"title" EDN for new link. |
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FPGA makes simple FIFO - 26-Oct-00 Issue of EDN-Design Ideas.....The circuit
in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and
write operations. The circuit can generate FIFO-occupancy flags with a minimum of
logic. The boxed area in Figure 1 shows a more conventional occupancy meter. The
circuit is implemented in a demultiplexer that writes data in the FIFO when the data
arrives and reads data according to FIFO occupancy.....PDF contains several circuits,
scroll to find this one..... [Design by Luis Miguel Brugolaras, SIRE, Madrid, Spain] |
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FPGA or DSP - (added 5/08) |
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FPGA Transfers Data on Every Clock Cycle - 03/03/94 EDN-Design Ideas.....The
circuit in Fig 1 uses the Actel 1240's latches in a static-RAM (SRAM) interface.
This interface transfers data on every clock cycle using a minimum of logic. (The
counter macro in the figure exists solely to provide sequential addresses.).....
[Design Idea by Gary Peyrot, Three Step Development, West Hills, CA] |
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FPGA-configuration scheme is flexible - 22-Jan-04 Issue of EDN FPGAs
are popular in circuit design because of their flexibility and efficiency. You need to
program an FPGA by loading configuration data into designated configuration memory.
Because most FPGAs have no internal nonvolatile memory, you must store the
configuration files in external devices. When you use many FPGAs in a design, it is
inadvisable to put a large amount of external memories near t..... [Design Idea by Zhe
Lou, Ghent University, Ghent, Belgium] |
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FPGA's Tri State Buffers Build 32x32 Crossbar - 12/08/94 EDN-Design
Ideas..... EDN is migrating links. This link is not verified. Search the "title"
EDN for new link. |
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Introduction to XS Volt Board Designs - done by the University of Queensland
(added 4/02) |
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| Gate Arrays:
#'s - B, C,
D - I, J - P,
Q - U,
V - Z |
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