Page 3 Gate Array Electronic Circuits

Gate Array Circuits Page 3
Gate Arrays: #'s - B, C, D - I, J - P, Q - U, V - Z
Last Updated on: Friday, February 05, 2010 10:05 AM

Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

Data Transfers to a Host PC or a processor based module - (added 5/08)

Data Unpacking Techniques for C6000 Systems - (added 5/08)

DDC with FPGA (using HERON-IO2V) - (added 5/08)

DDS with HERON FPGA - (added 5/08)

Developing a real time system-an example - The system will be dealing with data that comes from the real world. To begin with we will replace that data with a simple count so that we can check it’s correctness as it passes through the system. I chose to use an external clock to generate the data samples. Then I could easily change the data rate each time I wanted to establish the limit of performance of the system.....(added 5/08)

Digital Camera Interface - project shows how a CMOS ‘Camera On a Chip’ image sensor can be interfaced to an XSA-100 Board through an I2C bus. The pixel data is buffered in the XSA-100 SDRAM and is then uploaded through the parallel port to be displayed on a PC. (added 4/02)

Digital Down Conversion theory - (added 5/08)

Dual Output Supply Powers FPGAs from 3.3V & 5V Inputs - DN311 Design Notes (Linear Technology) (app note added 1/06)

External Memory Types for 'C6000 Systems - (added 5/08)

External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs - National Semiconductor Application Note (app note added 6/06)

Fast Integer Multipliers Fit in FPGAs - 05/12/94 EDN-Design Ideas: (design idea added 2/06)

FIFO Provides Data Width Conversion - 09/26/02 EDN-Design Ideas: Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1).....(design idea added 1/05)

Filters with HERON FPGA - (added 5/08)

FPGA Circuit Emulates 74x74 Flip Flop - 10/12/95 EDN-Design Ideas:.....(design idea added 11/05)

FPGA configuration scheme is flexible - 01/22/04 EDN-Design Ideas: (design idea added 1/05)

FPGA Configures Simple BCD Adder - 02/15/96 EDN-Design Ideas:.....(design idea added 11/05)

FPGA Implements X50 Division 3 Recommendation - 04/13/00 EDN-Design Ideas: The scheme in Figure 1a uses five delay cells and an XOR gate to configure the data stream for the X.50 Division 3 recommendation of ITU-T. The X.50 recommendation defines the fundamental parameters of a multiplexing scheme for interworking data networks using different envelope structures. Division 3 applies to the interworking between two networks, both of which use the 8-bit envelope structure.....(design idea added 10/05)

FPGA makes simple FIFO - 10/26/00 EDN-Design Ideas: The circuit in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and write operations. The circuit can generate FIFO-occupancy flags with a minimum of logic. The boxed area in Figure 1 shows a more conventional occupancy meter. The circuit is implemented in a demultiplexer that writes data in the FIFO when the data arrives and reads data according to FIFO occupancy.....(design idea added 4/02)

FPGA or DSP - (added 5/08)

FPGA Transfers Data on Every Clock Cycle - 03/03/94 EDN-Design Ideas:.....(design idea added 2/06)

FPGA's Tri State Buffers Build 32x32 Crossbar - 12/08/94 EDN-Design Ideas: (design idea added 2/06)

Introduction to XS Volt Board Designs - done by the University of Queensland (added 4/02)

Gate Arrays: #'s - B, C, D - I, J - P, Q - U, V - Z