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Gate Array Circuits
Page 4
Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z
Last Updated on:
Monday, October 03, 2011 06:07 PM |
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Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
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JBITS XHWIF Interface - for the XS40-005XL Board. (added 4/02)
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JBITS XHWIF Interface #2 - for the XSV-100 Board. (added 4/02)
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Loadable LED Register - showing the interaction between the
microcontroller and the CPLD or FPGA on the XS Board. (added 4/02)
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Look Ahead Approach Tames Large FPGA Counters - 12/22/94 EDN-Design
Ideas..... EDN is migrating links. This link is not verified. Search
the "title" EDN for new link. |
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Macro - that combines a complete USB transaction layer with an
8051 microcontroller core and a functional block that implements the
application-specific functions. This macro was developed and is
supported by Trenz Electronics for use with an XSV Board. (added 4/02)
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Measuring Jitter in Digital Systems AN 1448-1 - Agilent
Application Note (added 6/06) |
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Midrange device includes SERDES function - 09/19/06 EDN-Design
Ideas.....Lattice Semiconductor has announced a midcapacity, midpriced
FPGA ..... EDN is migrating links. This link is not verified. Search
the "title" EDN for new link. |
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Modulator's Design Cuts FPGA's Gate Count - 01/06/94 Issue of EDN-Design
Ideas.....The pulse-width modulator (PWM]macro in Fig 1 requires only half as much
logic as a conventional 2-counter design. With the help of extra logic, a synchronous,
loadable up/down counter can encode information in the duty cycle of a
constant-frequency, constant-amplitude signal..... [Design Idea by Bernie New, Xilinx,
San Jose, CA] |
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PC to SRAM Interface - for the XSV Board (Univ. of Queensland) (added 4/02)
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PC/XS Transfer - A circuit and C code for bidirectional transfer of data
between an XS40 Board and a PC. (added 4/02) |
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PC's parallel Port & a PLD host multiple stepper-motors & switches -
02/16/06 EDN-Design Ideas.....Well-suited for robotics applications requiring motion
in several direction..... EDN is migrating links. This link is not verified.
Google the "title" EDN for new link. |
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Plastic Pin Grid Array PPGA - National Semiconductor Application Note
(app note added 2/06) |
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PLL implements FPGA-based SDRAM controller - 03/26/98 EDN-Design
Ideas.....As FPGA capabilities increase and time to market decreases, FPGAs gain more
acceptance for implementing both data and control paths. Thus, they find wide use as
controllers and datapath glue logic for fast-page DRAMs. Synchronous DRAMs (SDRAMs),
whose control signals use a clock input as reference, are a natural target for FPGA-based
controllers…. [Design Idea by Eddy Debaere, Barco Graphics, Ghent, Belgium] |
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Priority Encoders Slip into FPGAs - 02/17/94 EDN-Design Ideas.....The
standard 8-to-3 priority encoder's design, in maximal canonical form (such as the
74148], suffers from drawbacks when you try to use the design as a macro in a large
digital project. The drawbacks are..... [Design Idea by Swapnajit Mittra, Baharat
Electronics, Bangalore, India] |
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PS/2 Interface - for the XSV Board (Univ. of Queensland) (added 4/02)
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| Gate Arrays:
#'s - B, C,
D - I, J - P,
Q - U,
V - Z |
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