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Gate Array Circuits Page 4
Gate Arrays:  #'s - B,    C,    D - I,    J - P,    Q - U,  
V - Z
Last Updated on: Friday, March 12, 2010 12:07 PM

 

Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

JBITS XHWIF Interface - for the XS40-005XL Board. (added 4/02)
JBITS XHWIF Interface #2 - for the XSV-100 Board. (added 4/02)
Loadable LED Register - showing the interaction between the microcontroller and the CPLD or FPGA on the XS Board. (added 4/02)
Look Ahead Approach Tames Large FPGA Counters - 12/22/94 EDN-Design Ideas: (design idea added 2/06)
Macro - that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions. This macro was developed and is supported by Trenz Electronics for use with an XSV Board. (added 4/02)
Measuring Jitter in Digital Systems AN 1448-1 - Agilent Application Note  (added 6/06)
Midrange device includes SERDES function - 09/19/06 EDN-Design Ideas: Lattice Semiconductor has announced a midcapacity, midpriced FPGA that includes some of the high-speed, high-end functions you typically only find in the most advanced and priciest Xilinx Virtex and Altera Stratix FPGAs. (design.....(design idea added 05/06/07)
Modulator's Design Cuts FPGA's Gate Count - 01/06/94 EDN-Design Ideas: The pulse-width modulator (PWM)macro in Fig 1 requires only half as much logic as a conventional 2-counter design. With the help of extra logic, a synchronous, loadable up/down counter can encode information in the duty cycle of a constant-frequency, constant-amplitude signal.....(design idea added 6/06)
PC to SRAM Interface - for the XSV Board (Univ. of Queensland) (added 4/02)
PC/XS Transfer - A circuit and C code for bidirectional transfer of data between an XS40 Board and a PC. (added 4/02)
PC's parallel Port & a PLD host multiple stepper motors & switches - 02/16/06 EDN-Design Ideas: Well-suited for robotics applications requiring motion in several direction.....(design idea added 10/06)
Plastic Pin Grid Array PPGA - National Semiconductor Application Note  (app note added 2/06)
PLL Implements FPGA Based SDRAM Controller  - 05/21/98 EDN-Design Ideas:  As FPGA capabilities increase and time to market decreases, FPGAs gain more acceptance for implementing both data and control paths. Thus, they find wide use as controllers and datapath glue logic for fast-page DRAMs. Synchronous DRAMs (SDRAMs),.....(design idea added 2/06)
Priority Encoders Slip into FPGAs - 02/17/94 EDN-Design Ideas:.....(design idea added 2/06)
PS/2 Interface - for the XSV Board (Univ. of Queensland) (added 4/02)
 

 
Gate Arrays:  #'s - B,    C,    D - I,    J - P,    Q - U,   V - Z
 
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