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Gate Array Circuits
Page 5
Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z
Last Updated on:
Friday, March 12, 2010 12:07 PM |
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Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
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Quick Draw - The object of Quick Draw is to test your reaction time against
your opponent's. A third person acts as a referee and begins the duel by pressing
S1, which lights LED1. Upon seeing LED1 go on, you try to outdraw your opponent by
….(added 05/08) |
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RISC µP Implements Fast FIR Filter - 01/21/99 EDN-Design Ideas: When it comes
to implementing a fast FIR filter, current RISC µPs can compete with DSP µPs. The
FIR algorithm continuously implements the following equation: N=n–1 Out=Sum[in(t[-]n)coeff(n)]
N=0,.....(design idea added 11/05) |
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RISC µP Supports IEEE Parallel Port Standard - 01/18/96 EDN-Design Ideas:
(design idea added 11/05) |
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Sampling of Signals for Digital Filtering & Gated Measurements - DN2
Design Notes (Linear Technology) (app note added 1/06) |
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Scheme Adds sequencing & shutdown Control to regulator - 10/30/03 EDN-Design
Ideas: Modern microprocessor or FP-GA-based circuits require separate and
independent power-supply voltages for the core and the I/O circuits. Some devices
require stringent control of the turn-on characteristics and sequencing of these
multiple power supplies to avoid internal parasitic current flows and consequent
latch-ups.....(design idea added 1/05) |
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SDRAM Controller Module - for the XSA-50 and XSA-100 Board that makes the
SDRAM look like a simple static RAM. (added 4/02) |
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SDRAM interface slashes pin count - 03/29/01 EDN-Design Ideas: Many designs
need deep buffering but don't require ultrahigh-memory bandwidth. Examples include
image and audio processing, as well as some deep-FIFO applications. These designs
often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach
solves the buffering problem but also burns a lot of valuable pins, which can be
as many as 27 for a single SDRAM device.....(design idea added 04/01) |
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Simple Circuit Provides Power Sequencing - 10/14/04 EDN-Design Ideas: AS
ICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on
their start-up sequencing. Often, I/O voltages, which usually have the highest
voltage, must come up first, followed by all other voltage rails in a high-to-low
order, with the core voltage last. This scenario may.....(design idea added
10/05) |
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Simple FIFO provides data width Conversion - 09/26/02 EDN-Design Ideas:
(design idea added 1/05) |
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Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z |
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