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Gate Array Circuits
Page 5
Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z
Last Updated on:
Monday, October 03, 2011 06:07 PM |
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Links to electronic circuits,
electronic schematics, designs for engineers, hobbyists, students & inventors:
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Quick Draw - The object of Quick Draw is to test your reaction
time against your opponent's. A third person acts as a referee and begins
the duel by pressing S1, which lights LED1. Upon seeing LED1 go on, you
try to outdraw your opponent by ….(added 05/08) |
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RISC µP implements fast FIR filter - 01/21/99 Issue of EDN
When it comes to implementing a fast FIR filter, current RISC µPs can
compete with DSP µPs......Page includes several designs. Scroll to
find this one..... [Design Idea by Sorin Zarnescu, NEC Electronics, Santa
Clara, CA] |
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RISC µP Supports IEEE Parallel Port Standard - 01/18/96 EDN-Design
Ideas..... EDN is migrating links. This link is not verified. Search
the "title" EDN for new link. |
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Sampling of Signals for Digital Filtering & Gated Measurements -
DN2 Design Notes (Linear Technology) (app note added 1/06)
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Scheme adds sequencing and shutdown control to regulator -
30-Oct-03 Issue of EDN Modern microprocessor- or FP-GA-based
circuits require separate and independent power-supply voltages for the
core and the I/O circuits..... [Design Idea by Said Jackson, Equator
Technologies Inc, Campbell, CA] |
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SDRAM Controller Module - for the XSA-50 and XSA-100 Board that makes the
SDRAM look like a simple static RAM. (added 4/02) |
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SDRAM interface slashes pin count - 03/29/01 EDN-Design Ideas.....Many
designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples
include image and audio processing, as well as some deep-FIFO applications. These
designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This
approach solves the buffering problem but also burns a lot of valuable pins, which can
be as many as 27 for a single SDRAM device..... EDN is migrating links. This link is
not verified. Google the "title" EDN for new link. |
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Simple circuit provides power sequencing - 14-Oct-04 Issue of EDN
ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their
start-up sequencing. Often, I/O voltages, which usually have the highest voltage, must
come up first, followed by all other voltage rails in a high-to-low order, with the
core voltage last. This scenario may also require that one supply rail not
exceed another bythan a diode drop; otherwise, excessive c..... [Design Idea by John
Betten, Texas Instruments, Dallas, TX] |
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Simple FIFO provides data width conversion - 26-Sep-02 Issue of EDN
Many designs require FIFO elastic buffers to form a bridge between subsystems with
different clock rates and access requirements. However, in some applications, you need
FIFO buffers for data conversion. One example is the case in which you need to connect
an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1].....
[Design Idea by David Lou, Ghent University, Ghent, Belgium] |
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Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux -
National Semiconductor Application Note (app note added 2/06) |
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Speed FPGA Debug with Mixed-Signal Oscilloscopes - Agilent Application
Note.....[App Note] |
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SRAM Interface - for the XSV Board (Univ. of Queensland) (added 4/02)
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Stereo Loopback Circuit - that accepts a digitized stereo signal from the
ADC of the XStend Board codec and loops the signal back to the codec DAC stage for
output as a stereo signal. (added 4/02) |
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Swapping bits improves performance of FPGA PWM counter - 13-Sep-07 Issue of
EDN A simple change to the specification of an FPGA counter lowers the ripple of
a PWM counter functioning as a DAC..... [Design Idea by Stefaan Vanheesbeke, Ledegem,
Belgium] |
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Tool generates HDLs directly from Simulink - 09/19/06 EDN-Design
Ideas.....The folks trying to model multiple DSP functions to implement in FPGAs or
ASICs using MathWorks tools will be happy to learn that the company's latest release,
Simulink HDL Coder, automatically generates cycle-accurate, bit-accurate Verilog or
VHDL directly from Simulink..... [Design Idea by Michael Santarini, Senior Editor --
EDN] |
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Two wires control SPI high-speed ADC - 10-Nov-05 Issue of EDN
Inverters substitute for an SPI ADC's chip-select line..... [Design Idea by Dan Meeks,
Texas Instruments Inc, Austin, TX; Edited by Brad Thompson and Fran Granville] |
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USB Macro - that combines a complete USB transaction layer with an 8051
microcontroller core and a functional block that implements the application-specific
functions. This macro was developed and is supported by Trenz Electronics for
use with an XSV Board. (added 4/02) |
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Using an SZ Volt Board Xchecker Interface - Zess Corporation / Application
Notes / configures the CPLD on the XSV Board so the By checker interface is enabled.
(added 4/02) |
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Using the 16700 Logic Analyzer with the Xilinx ChipScope ILA - Agilent
Application Note (added 6/06) |
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Gate Arrays: #'s - B,
C, D - I,
J - P, Q - U,
V - Z |
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